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參數(shù)資料
| 型號(hào)： | A5191HRTPG-XTP |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MODEM HART SGL CMOS 28PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 數(shù)據(jù)格式： | HART |
| 波特率： | 1.2k |
| 電源電壓： | 3 V ~ 5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | A5191HRTPG-XTPOSDKR |
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A5191HRT
http://onsemi.com
10
Internal Oscillator Option
The oscillator cell will function with either a 460.8 kHz
crystal or ceramic resonator. A parallel resonant ceramic
resonator can be connected between XIN and XOUT.
Figure 12 illustrates the crystal option for clock generation
using a 460.8 kHz (
±1 % tolerance) parallel resonant crystal
and two tuning capacitors Cx. The actual values of the
capacitors may depend on the recommendations of the
manufacturer of the resonator. Typically, capacitors in the
range of 100 pF to 470 pF are used.
XOUT
XIN
CX
460.8 kHz
Crystal
Oscillator
Figure 12. Crystal Oscillator
External Clock Option
It may be desirable to use an external 460.8 kHz clock as
shown in Figure 13 rather than the internal oscillator. In
addition, the A5191HRT consumes less current when an
external clock is used. Minimum current consumption
occurs with the clock connected to XOUT and XIN
connected to VSS.
XOUT
XIN
Crystal
Oscillator
460.8 kHz
Figure 13. Oscillator with External Clock
Power On Reset
During start-up the RESETB pin should be kept low until
the voltage level on VDD is above the minimum level VDDH
= 2.5 V to guarantee correct operation of the digital circuitry.
As illustrated in Figure 14 RESETB should be kept low for
at least tPOR = 10 ns after this threshold level is reached.
tPOR =10 ns
VDDH =2.5 V
VDD
t
RESET pin
Figure 14. Power On Reset Timing
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