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參數(shù)資料
| 型號： | A54SX08-1PL84I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 64/64頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA SX 12K GATES 84-PLCC |
| 標準包裝： | 16 |
| 系列： | SX |
| LAB/CLB數(shù)： | 768 |
| 輸入/輸出數(shù)： | 69 |
| 門數(shù)： | 12000 |
| 電源電壓： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應商設備封裝： | 84-PLCC（29.31x29.31） |
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SX Family FPGAs
v3.2
1-5
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring R-
cell in a given SuperCluster. DirectConnect uses a
hardwired signal path requiring no programmable
interconnection to achieve its fast signal propagation
time of less than 0.1 ns.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect
path,
delivering
maximum
pin-to-pin
propagation of 0.4 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. The Actel segmented routing structure provides
a variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
100 percent automatic place-and-route software to
minimize signal propagation delays.
The Actel high-drive routing structure provides three
clock networks. The first clock, called HCLK, is hardwired
from the HCLK buffer to the clock select multiplexer
(MUX) in each R-cell. This provides a fast propagation
path for the clock signal, enabling the 3.7 ns clock-to-out
(pin-to-pin)
performance
of
the
SX
devices.
The
hardwired clock is tuned to provide clock skew as low as
0.25 ns. The remaining two clocks (CLKA, CLKB) are
global clocks that can be sourced from external pins or
from internal logic signals within the SX device.
Other Architectural Features
Technology
The Actel SX family is implemented on a high-voltage
twin-well CMOS process using 0.35 design rules. The
metal-to-metal antifuse is made up of a combination of
amorphous silicon and dielectric material with barrier
metals and has a programmed ("on" state) resistance of
25
Ω with a capacitance of 1.0 fF for low signal impedance.
Performance
The combination of architectural features described
above enables SX devices to operate with internal clock
frequencies exceeding 300 MHz, enabling very fast
execution of even complex logic functions. Thus, the SX
family is an optimal platform upon which to integrate
the functionality previously contained in multiple CPLDs.
In addition, designs that previously would have required
a gate array to meet performance goals can now be
integrated
into
an
SX
device
with
dramatic
improvements in cost and time to market. Using timing-
driven place-and-route tools, designers can achieve
highly
deterministic
device
performance.
With
SX
devices, designers do not need to use complicated
performance-enhancing design techniques such as the
use of redundant logic to reduce fanout on critical nets
or the instantiation of macros in HDL code to achieve
high performance.
I/O Modules
Each I/O on an SX device can be configured as an input,
an output, a tristate output, or a bidirectional pin.
Even without the inclusion of dedicated I/O registers,
these I/Os, in combination with array registers, can
achieve clock-to-out (pad-to-pad) timing as fast as 3.7 ns.
I/O cells that have embedded latches and flip-flops
require instantiation in HDL code; this is a design
complication not encountered in SX FPGAs. Fast pin-to-
pin timing ensures that the device will have little trouble
interfacing with any other device in the system, which in
turn enables parallel design of system components and
reduces overall design time.
Power Requirements
The SX family supports 3.3 V operation and is designed
to tolerate 5.0 V inputs. (Table 1-1). Power consumption
is extremely low due to the very short distances signals
are required to travel to complete a circuit. Power
requirements are further reduced because of the small
number of low-resistance antifuses in the path. The
antifuse architecture does not require active circuitry to
hold a charge (as do SRAM or EPROM), making it the
lowest power architecture on the market.
Table 1-1
Supply Voltages
Device
VCCA
VCCI
VCCR
Maximum Input Tolerance
Maximum Output Drive
A54SX08
A54SX16
A54SX32
3.3 V
5.0 V
3.3 V
A54SX16-P*
3.3 V
5.0 V
3.3 V
5.0 V
Note: *A54SX16-P has three different entries because it is capable of both a 3.3 V and a 5.0 V drive.
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| A54SX08-1PLG84 | 功能描述:IC FPGA SX 12K GATES 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
| A54SX08-1PLG84I | 功能描述:IC FPGA SX 12K GATES 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
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