Table 1-20 A54SX32 Timing Characteristics (Worst-Case Commercial Con" />
參數(shù)資料
型號(hào)： A54SX08-2VQG100I
廠商： Microsemi SoC
文件頁數(shù)： 29/64頁
文件大?。?/td> 0K
描述： IC FPGA SX 12K GATES 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： SX
LAB/CLB數(shù)： 768
輸入/輸出數(shù)： 81
門數(shù)： 12000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
SX Family FPGAs
v3.2
1-31
A54SX32 Timing Characteristics
Table 1-20 A54SX32 Timing Characteristics
(Worst-Case Commercial Conditions, VCCR= 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C)
Parameter
Description
'–3' Speed
'–2' Speed
'–1' Speed
'Std' Speed
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
C-Cell Propagation Delays1
tPD
Internal Array Module
0.6
0.7
0.8
0.9
ns
Predicted Routing Delays2
tDC
FO = 1 Routing Delay, Direct Connect
0.1
ns
tFC
FO = 1 Routing Delay, Fast Connect
0.3
0.4
0.5
ns
tRD1
FO = 1 Routing Delay
0.3
0.4
0.5
ns
tRD2
FO = 2 Routing Delay
0.7
0.8
0.9
1.0
ns
tRD3
FO = 3 Routing Delay
1.0
1.2
1.4
1.6
ns
tRD4
FO = 4 Routing Delay
1.4
1.6
1.8
2.1
ns
tRD8
FO = 8 Routing Delay
2.7
3.1
3.5
4.1
ns
tRD12
FO = 12 Routing Delay
4.0
4.7
5.3
6.2
ns
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.8
1.1
1.3
1.4
ns
tCLR
Asynchronous Clear-to-Q
0.5
0.6
0.7
0.8
ns
tPRESET
Asynchronous Preset-to-Q
0.7
0.8
0.9
1.0
ns
tSUD
Flip-Flop Data Input Set-Up
0.5
0.6
0.7
0.8
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tWASYN
Asynchronous Pulse Width
1.4
1.6
1.8
2.1
ns
Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
1.5
1.7
1.9
2.2
ns
tINYL
Input Data Pad-to-Y LOW
1.5
1.7
1.9
2.2
ns
Predicted Input Routing Delays2
tIRD1
FO = 1 Routing Delay
0.3
0.4
0.5
ns
tIRD2
FO = 2 Routing Delay
0.7
0.8
0.9
1.0
ns
tIRD3
FO = 3 Routing Delay
1.0
1.2
1.4
1.6
ns
tIRD4
FO = 4 Routing Delay
1.4
1.6
1.8
2.1
ns
tIRD8
FO = 8 Routing Delay
2.7
3.1
3.5
4.1
ns
tIRD12
FO = 12 Routing Delay
4.0
4.7
5.3
6.2
ns
Note:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH the loading is 5 pF.
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