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參數(shù)資料
| 型號(hào)： | A54SX08-3TQ176 |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁數(shù)： | 5/36頁 |
| 文件大?。?/td> | 833K |
| 代理商： | A54SX08-3TQ176 |
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v2.0
5
54SX Family FPGAs RadTolerant and HiRel
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to integrate
a 3-input exclusive-OR function into a single C-cell. This
facilitates construction of 9-bit parity-tree functions with 2
ns propagation delays. At the same time, the C-cell
structure is extremely synthesis-friendly, simplifying the
overall design and reducing synthesis time.
Chip Architecture
The
SX
uniqueapproach to module organization and chip routing
that delivers the best register/logic mix for a wide variety of
new and emerging applications.
family
’
s
chip
architecture
provides
a
Module Organization
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called
Clusters
. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into
SuperClusters
(see
Figure 5 on page 6
). SuperCluster 1 is a two-wide
grouping of Type 1 clusters. SuperCluster 2 is a two-wide
group containing one Type 1 cluster and one Type 2 cluster.
SX devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
more combinatorial logic than flip-flops.
Figure 2
Channelled Array and Sea-of-Modules Architectures
Figure 3
R-Cell
Channelled Array Architecture
Sea-of-Modules Architecture
Direct
Connect
Input
CLKA,
CLKB
HCLK
CKS
CKP
CLRB
PSET
Y
D
Q
Routed
Data Input
S0
S1
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| A54SX08-3VQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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