• <dfn id="wbqix"></dfn>
    •
    參數(shù)資料
    型號(hào)： A54SX08A-2FG144
    廠商： Microsemi SoC
    文件頁(yè)數(shù)： 20/108頁(yè)
    文件大小： 0K
    描述： IC FPGA SX 12K GATES 144-FBGA
    標(biāo)準(zhǔn)包裝： 160
    系列： SX-A
    LAB/CLB數(shù)： 768
    輸入/輸出數(shù)： 111
    門數(shù)： 12000
    電源電壓： 2.25 V ~ 5.25 V
    安裝類型： 表面貼裝
    工作溫度： 0°C ~ 70°C
    封裝/外殼： 144-LBGA
    供應(yīng)商設(shè)備封裝： 144-FPBGA（13x13）
    SX-A Family FPGAs
    v5.3
    1-15
    Pin Description
    CLKA/B, I/O
    Clock A and B
    These pins are clock inputs for clock distribution
    networks. Input levels are compatible with standard TTL,
    LVTTL, LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. The
    clock input is buffered prior to clocking the R-cells. When
    not used, this pin must be tied Low or High (NOT left
    floating) on the board to avoid unwanted power
    consumption.
    For A54SX72A, these pins can also be configured as user
    I/Os. When employed as user I/Os, these pins offer built-
    in programmable pull-up or pull-down resistors active
    during power-up only. When not used, these pins must
    be tied Low or High (NOT left floating).
    QCLKA/B/C/D, I/O
    Quadrant Clock A, B, C, and D
    These four pins are the quadrant clock inputs and are
    only
    used
    for
    A54SX72A
    with
    A,
    B,
    C,
    and
    D
    corresponding to bottom-left, bottom-right, top-left,
    and top-right quadrants, respectively. They are clock
    inputs for clock distribution networks. Input levels are
    compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V
    PCI, or 5 V PCI specifications. Each of these clock inputs
    can drive up to a quarter of the chip, or they can be
    grouped together to drive multiple quadrants. The clock
    input is buffered prior to clocking the R-cells. When not
    used, these pins must be tied Low or High on the board
    (NOT left floating).
    These pins can also be configured as user I/Os. When
    employed
    as
    user
    I/Os,
    these
    pins
    offer
    built-in
    programmable pull-up or pull-down resistors active
    during power-up only.
    GND
    Ground
    Low supply voltage.
    HCLK
    Dedicated (Hardwired)
    Array Clock
    This pin is the clock input for sequential modules. Input
    levels
    are
    compatible
    with
    standard
    TTL,
    LVTTL,
    LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. This input is
    directly wired to each R-cell and offers clock speeds
    independent of the number of R-cells being driven.
    When not used, HCLK must be tied Low or High on the
    board (NOT left floating). When used, this pin should be
    held Low or High during power-up to avoid unwanted
    static power consumption.
    I/O
    Input/Output
    The I/O pin functions as an input, output, tristate, or
    bidirectional buffer. Based on certain configurations,
    input and output levels are compatible with standard
    TTL, LVTTL, LVCMOS2, 3.3 V PCI or 5 V PCI specifications.
    Unused I/O pins are automatically tristated by the
    Designer software.
    NC
    No Connection
    This pin is not connected to circuitry within the device
    and can be driven to any voltage or be left floating with
    no effect on the operation of the device.
    PRA/B, I/O
    Probe A/B
    The Probe pin is used to output data from any user-
    defined design node within the device. This independent
    diagnostic pin can be used in conjunction with the other
    probe pin to allow real-time diagnostic output of any
    signal path within the device. The Probe pin can be used
    as a user-defined I/O when verification has been
    completed.
    The
    pin’s
    probe
    capabilities
    can
    be
    permanently disabled to protect programmed design
    confidentiality.
    TCK, I/O
    Test Clock
    Test clock input for diagnostic probe and device
    programming. In Flexible mode, TCK becomes active
    when the TMS pin is set Low (refer to Table 1-6 on
    page 1-9). This pin functions as an I/O when the
    boundary scan state machine reaches the "logic reset"
    state.
    TDI, I/O
    Test Data Input
    Serial input for boundary scan testing and diagnostic
    probe. In Flexible mode, TDI is active when the TMS pin is
    set Low (refer to Table 1-6 on page 1-9). This pin
    functions as an I/O when the boundary scan state
    machine reaches the “l(fā)ogic reset” state.
    TDO, I/O
    Test Data Output
    Serial output for boundary scan testing. In flexible mode,
    TDO is active when the TMS pin is set Low (refer to
    Table 1-6 on page 1-9). This pin functions as an I/O when
    the boundary scan state machine reaches the "logic
    reset" state. When Silicon Explorer II is being used, TDO
    will act as an output when the checksum command is
    run. It will return to user /IO when checksum is complete.
    TMS
    Test Mode Select
    The TMS pin controls the use of the IEEE 1149.1
    Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible
    mode when the TMS pin is set Low, the TCK, TDI, and
    TDO pins are boundary scan pins (refer to Table 1-6 on
    page 1-9). Once the boundary scan pins are in test mode,
    they will remain in that mode until the internal
    boundary scan state machine reaches the logic reset
    state. At this point, the boundary scan pins will be
    released and will function as regular I/O pins. The logic
    reset state is reached five TCK cycles after the TMS pin is
    set High. In dedicated test mode, TMS functions as
    specified in the IEEE 1149.1 specifications.
    TRST, I/O
    Boundary Scan Reset Pin
    Once it is configured as the JTAG Reset pin, the TRST pin
    functions as an active low input to asynchronously
    initialize or reset the boundary scan circuit. The TRST pin
    is equipped with an internal pull-up resistor. This pin
    functions as an I/O when the Reserve JTAG Reset Pin is
    not selected in Designer.
    VCCI
    Supply Voltage
    Supply voltage for I/Os. See Table 2-2 on page 2-1. All
    VCCI power pins in the device should be connected.
    VCCA
    Supply Voltage
    Supply voltage for array. See Table 2-2 on page 2-1. All
    VCCA power pins in the device should be connected.
    相關(guān)PDF資料
    PDF描述
    A54SX08A-1FGG144I IC FPGA SX 12K GATES 144-FBGA
    A54SX08A-1FG144I IC FPGA SX 12K GATES 144-FBGA
    A3PE600-1FGG484 IC FPGA 600000 GATES 484-FBGA
    A3PE600-1FG484 IC FPGA 600000 GATES 484-FBGA
    GSC36DTES CONN EDGECARD 72POS .100 EYELET
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    A54SX08A-2FG144I 功能描述:IC FPGA SX 12K GATES 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
    A54SX08A-2FG208 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs
    A54SX08A-2FG208A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs
    A54SX08A-2FG208B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs
    A54SX08A-2FG208I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs
    發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

    采購(gòu)需求

    (若只采購(gòu)一條型號(hào)，填寫一行即可)

    發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

    發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

    *型號(hào) *數(shù)量 廠商 批號(hào) 封裝
    添加更多采購(gòu)

    我的聯(lián)系方式

    *
    *
    *