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參數(shù)資料
| 型號(hào)： | A54SX08A-FTQG144 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 40/108頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA SX 12K GATES 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | SX-A |
| LAB/CLB數(shù)： | 768 |
| 輸入/輸出數(shù)： | 113 |
| 門數(shù)： | 12000 |
| 電源電壓： | 2.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
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SX-A Family FPGAs
v5.3
2-17
Timing Characteristics
Timing characteristics for SX-A devices fall into three
categories: family-dependent, device-dependent, and
design-dependent.
The
input
and
output
buffer
characteristics are common to all SX-A family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design are
complete. The timing characteristics listed in this
datasheet represent sample timing numbers of the SX-A
devices. Design-specific delay values may be determined
by using Timer or performing simulation after successful
place-and-route with the Designer software.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
timing-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to 6 percent of the nets in a design may be designated as
critical, while 90 percent of the nets in a design are
typical.
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules.
Long tracks employ three to five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6 percent of
nets in a fully utilized device require long tracks. Long
tracks contribute approximately 4 ns to 8.4 ns delay. This
additional delay is represented statistically in higher
fanout routing delays.
Timing Derating
SX-A devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum
operating
temperature,
and
best-case
processing.
Maximum
timing
parameters
reflect
minimum
operating
voltage,
maximum
operating
temperature, and worst-case processing.
Temperature and Voltage Derating Factors
Table 2-13 Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 2.25 V)
VCCA
Junction Temperature (TJ)
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
2.250 V
0.790.800.870.89
1.001.04
1.14
2.500 V
0.740.750.820.83
0.940.97
1.07
2.750 V
0.680.690.750.77
0.870.90
0.99
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX08A-FTQG208 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs |
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| A54SX08A-FTQG208B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs |
| A54SX08A-FTQG208I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs |
| A54SX08A-FTQG208M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs |
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