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| 型號： | A54SX08AFG144I |
| 英文描述： | Logic IC |
| 中文描述： | 邏輯IC |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 833K |
| 代理商： | A54SX08AFG144I |
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54SX Family FPGAs RadTolerant and HiRel
4
v2.0
SX Family Architecture
The SX family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
Programmable Interconnect Element
Actel
’
s SX family provides much more efficient use of silicon
by locating the routing interconnect resources between the
Metal 2 (M2) and Metal 3 (M3) layers (
Figure 1
). This
completely eliminates the channels of routing and
interconnect resources between logic modules (as
implemented on SRAM FPGAs and previous generations of
antifuse FPGAs), and enables the entire floor of the device
to be spanned with an uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using Actel
’
s patented metal-to-metal programmable
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives the SX family abundant routing resources and provides
excellent protection against design pirating. Reverse
engineering is virtually impossible, because it is extremely
difficult to distinguish between programmed and
unprogrammed antifuses, and there is no configuration
bitstream to intercept.
Additionally, the interconnects (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
Logic Module Design
The SX family architecture has been called a
“
sea-of-modules
”
architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing (see
Figure 2 on page 5
). Actel provides two types of
logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring more control signals
than
in
previous
Actel
asynchronous clear, asynchronous preset, and clock enable
(using the S0 and S1 lines). The R-cell registers feature
architectures,
including
programmable
register-by-register basis (
Figure 3 on page 5
). This provides
the designer with additional flexibility while allowing
mapping of synthesized functions into the SX FPGA. The
clock source for the R-cell can be chosen from the
hard-wired clock or the routed clock.
The C-cell implements a range of combinatorial functions
up to 5-inputs (
Figure 4 on page 6
). Inclusion of the DB
input and its associated inverter function dramatically
increases the number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
clock
polarity,
selectable
on
a
Figure 1
SX Family Interconnect Elements
Silicon Substrate
Tungsten Plug
Contact
Metal 1
Metal 2
Metal 3
Routing Tracks
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A54SX08AFG144M | Logic IC |
| A54SX08-FG144 | Field Programmable Gate Array (FPGA) |
| A54SX08-FG144I | Field Programmable Gate Array (FPGA) |
| A54SX08-PL84 | Field Programmable Gate Array (FPGA) |
| A54SX08-PL84I | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX08A-FG144I | 功能描述:IC FPGA SX 12K GATES 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A54SX08AFG144M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| A54SX08A-FG208 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs |
| A54SX08AFG208A | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs |
| A54SX08A-FG208A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs |
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