參數(shù)資料
型號： A54SX08P-1FG208M
廠商： Electronic Theatre Controls, Inc.
英文描述： TV 128C 128#22D SKT RECP
中文描述： 54SX家庭的FPGA
文件頁數(shù)： 26/57頁
文件大?。?/td> 415K
代理商： A54SX08P-1FG208M
5 4 S X F a m ily F P G A s
26
v3.1
A 5 4 S X 0 8 T im ing C ha ra c t e ris t ic s
(c ontinue d)
(Wors t-C a s e C omme rc ia l C onditions )
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Dedicated (Hard-Wired) Array Clock Network
t
HCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.0
1.1
1.3
1.5
ns
t
HCKL
Input HIGH to LOW
(Pad to R-Cell Input)
1.0
1.2
1.4
1.6
ns
t
HPWH
t
HPWL
t
HCKSW
t
HP
f
HMAX
Minimum Pulse Width HIGH
1.4
1.6
1.8
2.1
ns
Minimum Pulse Width LOW
1.4
1.6
1.8
2.1
ns
Maximum Skew
0.1
0.2
0.2
0.2
ns
Minimum Period
2.7
3.1
3.6
4.2
ns
Maximum Frequency
350
320
280
240
MHz
Routed Array Clock Networks
t
RCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
1.3
1.5
1.7
2.0
ns
t
RCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
1.4
1.6
1.8
2.1
ns
t
RCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
1.4
1.7
1.9
2.2
ns
t
RCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
1.5
1.7
2.0
2.3
ns
t
RCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
1.5
1.7
1.9
2.2
ns
t
RCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
1.5
1.8
2.0
2.3
ns
t
RPWH
t
RPWL
t
RCKSW
t
RCKSW
t
RCKSW
TTL Output Module Timing
1
Min. Pulse Width HIGH
2.1
2.4
2.7
3.2
ns
Min. Pulse Width LOW
2.1
2.4
2.7
3.2
ns
Maximum Skew (Light Load)
0.1
0.2
0.2
0.2
ns
Maximum Skew (50% Load)
0.3
0.3
0.4
0.4
ns
Maximum Skew (100% Load)
0.3
0.3
0.4
0.4
ns
t
DLH
t
DHL
t
ENZL
t
ENZH
t
ENLZ
t
ENHZ
Note:
1.
Data-to-Pad LOW to HIGH
1.6
1.9
2.1
2.5
ns
Data-to-Pad HIGH to LOW
1.6
1.9
2.1
2.5
ns
Enable-to-Pad, Z to L
2.1
2.4
2.8
3.2
ns
Enable-to-Pad, Z to H
2.3
2.7
3.1
3.6
ns
Enable-to-Pad, L to Z
1.4
1.7
1.9
2.2
ns
Enable-to-Pad, H to Z
1.3
1.5
1.7
2.0
ns
Delays based on 35 pF loading, except t
ENZL
and t
ENZH
. For t
ENZL
and t
ENZH
the loading is 5 pF.
相關(guān)PDF資料
PDF描述
A54SX08P-1FG208PP TV 128C 128#22D SKT RECP
A54SX08P-1PL208 Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVP00; No. of Contacts:128; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight
A54SX08P-1PL208I Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVP00; Number of Contacts:128; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight
A54SX08P-1PL208M Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVP00; Number of Contacts:128; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight
A54SX08P-1PL208PP Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVP00; No. of Contacts:128; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A54SX08P-1FG208PP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs
A54SX08P-1FGG208 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs
A54SX08-P-1FGG208I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs
A54SX08P-1FGG208I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs
A54SX08-P-1FGG208M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs
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