參數(shù)資料
型號: A54SX08P-PL208I
廠商: Electronic Theatre Controls, Inc.
英文描述: LM1877 Dual Audio Power Amplifier; Package: SOIC WIDE; No of Pins: 14; Qty per Container: 50; Container: Rail
中文描述: 54SX家庭的FPGA
文件頁數(shù): 31/57頁
文件大小: 415K
代理商: A54SX08P-PL208I
v3.1
31
5 4 S X F a m ily F P G A s
A 5 4 S X 1 6 P T im ing C ha ra c t e ris t ic s
(c ontinue d)
(Wors t-C a s e C omme rc ia l C onditions V
C C R
= 3 .0V , V
C C A
, V
C C I
= 3.0V , T
J
= 70°C )
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
PCI Output Module Timing
1
t
DLH
t
DHL
t
ENZL
t
ENZH
t
ENLZ
t
ENHZ
Data-to-Pad LOW to HIGH
1.8
2.0
2.3
2.7
ns
Data-to-Pad HIGH to LOW
1.7
2.0
2.2
2.6
ns
Enable-to-Pad, Z to L
0.8
1.0
1.1
1.3
ns
Enable-to-Pad, Z to H
1.2
1.2
1.5
1.8
ns
Enable-to-Pad, L to Z
1.0
1.1
1.3
1.5
ns
Enable-to-Pad, H to Z
1.1
1.3
1.5
1.7
ns
TTL Output Module Timing
t
DLH
t
DHL
t
ENZL
t
ENZH
t
ENLZ
t
ENHZ
Note:
1.
Data-to-Pad LOW to HIGH
2.1
2.5
2.8
3.3
ns
Data-to-Pad HIGH to LOW
2.0
2.3
2.6
3.1
ns
Enable-to-Pad, Z to L
2.5
2.9
3.2
3.8
ns
Enable-to-Pad, Z to H
3.0
3.5
3.9
4.6
ns
Enable-to-Pad, L to Z
2.3
2.7
3.1
3.6
ns
Enable-to-Pad, H to Z
2.9
3.3
3.7
4.4
ns
Delays based on 10 pF loading.
相關(guān)PDF資料
PDF描述
A54SX08P-PL208M 54SX Family FPGAs
A54SX08P-PL208PP LM1877 Dual Audio Power Amplifier; Package: MDIP; No of Pins: 14; Qty per Container: 25; Container: Rail
A54SX08P-PQ208 LM1881 Video Sync Separator; Package: SOIC NARROW; No of Pins: 8; Qty per Container: 95; Container: Rail
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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A54SX08P-PL208PP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs
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A54SX08P-PQ208I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs
A54SX08P-PQ208M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs