參數(shù)資料
型號(hào)： A54SX16-CQ256M
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA）
文件頁(yè)數(shù)： 10/36頁(yè)
文件大小： 833K
代理商： A54SX16-CQ256M
54SX Family FPGAs RadTolerant and HiRel
10
v2.0
machine reaches the
“
logic reset
”
state. At this point the
BST pins will be released and will function as regular I/O
pins. The "logic reset
”
state is reached 5 TCK cycles after
the TMS pin is set to logical HIGH.
The program fuse determines whether the device is in
Dedicated Test or Flexible mode. The default (fuse not
programmed) is Flexible mode.
Development Tool Support
The RT54SX RadTolerant devices are fully supported by
Actel
’
s line of FPGA development tools, including the Actel
DeskTOP Series and Designer Series
’
tools. The Actel
DeskTOP Series is an integrated design environment for PCs
that includes design entry, simulation, synthesis, and
place-and-route tools. Designer Series is Actel
’
s suite of
FPGA development point tools for PCs and Workstations
that includes the ACTgen Macro Builder, Designer Series
with DirectTime timing driven place-and-route and analysis
tools, and device programming software.
RT54SX Probe Circuit Control Pins
The RT54SX RadTolerant devices contain internal probing
circuitry that provides built-in access to every node in a
design, enabling 100-percent real-time observation and
analysis of a device's internal logic nodes without design
iteration. The probe circuitry is accessed by Silicon Explorer
II, an easy to use integrated verification and logic analysis
tool that can sample data at 100 MHz (asynchronous) or
66 MHz (synchronous). Silicon Explorer attaches to a PC
’
s
standard COM port, turning the PC into a fully functional 18
channel logic analyzer. Silicon Explorer allows designers to
complete the design verification process at their desks and
reduces verification time from several hours per cycle to a
few seconds.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TRST, TCK, TMS, and TDO) to select the desired nets
for verification. The selected internal nets are assigned to
the PRA/PRB pins for observation.
Figure 11
illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification.
Design Considerations
For prototyping, the TDI, TCK, TDO, PRA, and PRB pins
should not be used as input or bidirectional ports. Because
these pins are active during probing, critical signals input
through these pins are not available while probing. In
addition, the security fuse should not be programmed during
prototyping because doing so disables the probe circuitry.
Figure 11
Probe Setup
Silicon Explorer II
TCK
TMS
TDO
PRA
PRB
Serial Connection
1
C
RT54SX-S FPGA
TRST
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