Table 1-8 A54SX16P DC Specifications (3.3 V PCI Operation) Symbol " />
參數(shù)資料
型號: A54SX16P-1PQG208M
廠商: Microsemi SoC
文件頁數(shù): 8/64頁
文件大?。?/td> 0K
描述: IC FPGA SX 24K GATES 208-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: SX
LAB/CLB數(shù): 1452
輸入/輸出數(shù): 175
門數(shù): 24000
電源電壓: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: -55°C ~ 125°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
SX Family FPGAs
1- 12
v3.2
A54SX16P DC Specifications (3.3 V PCI Operation)
Table 1-8
A54SX16P DC Specifications (3.3 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
VCCA
Supply Voltage for Array
3.0
3.6
V
VCCR
Supply Voltage required for Internal Biasing
3.0
3.6
V
VCCI
Supply Voltage for I/Os
3.0
3.6
V
VIH
Input High Voltage
0.5VCC
VCC + 0.5
V
VIL
Input Low Voltage
–0.5
0.3VCC
V
IIPU
Input Pull-up Voltage1
0.7VCC
V
IIL
Input Leakage Current2
0 < VIN < VCC
±10
A
VOH
Output High Voltage
IOUT = –500 A
0.9VCC
V
VOL
Output Low Voltage
IOUT = 1500 A
0.1VCC
V
CIN
Input Pin Capacitance3
10
pF
CCLK
CLK Pin Capacitance
5
12
pF
CIDSEL
IDSEL Pin Capacitance4
8pF
Notes:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a
floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current
at this input voltage.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
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