PDC
參數(shù)資料
型號(hào): A54SX32-1TQ176
廠商: Microsemi SoC
文件頁(yè)數(shù): 15/64頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SX 48K GATES 176-TQFP
標(biāo)準(zhǔn)包裝: 40
系列: SX
LAB/CLB數(shù): 2880
輸入/輸出數(shù): 147
門數(shù): 48000
電源電壓: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 176-LQFP
供應(yīng)商設(shè)備封裝: 176-TQFP(24x24)
SX Family FPGAs
1- 18
v3.2
Step 3:
Calculate DC Power Dissipation
DC Power Dissipation
PDC = (Istandby) × VCCA + (Istandby) × VCCR + (Istandby) ×
VCCI + X × VOL × IOL + Y(VCCI – VOH) × VOH
EQ 1-12
For a rough estimate of DC Power Dissipation, only use
PDC =(Istandby) × VCCA. The rest of the formula provides a
very small number that can be considered negligible.
PDC = (Istandby) × VCCA
PDC = .55 mA × 3.3 V
PDC = 0.001815 W
Step 4:
Calculate Total Power Consumption
PTotal = PAC + PDC
PTotal = 1.461 + 0.001815
PTotal = 1.4628 W
Step 5:
Compare Estimated Power Consumption
against Characterized Power Consumption
The estimated total power consumption for this design is
1.46 W. The characterized power consumption for this
design at 200 MHz is 1.0164 W.
Step 1:
Define Terms Used in Formula
VCCA
3.3
Module
Number of logic modules switching
at fm (Used 50%)
m
264
Average logic modules switching rate
fm (MHz) (Guidelines: f/10)
fm
20
Module capacitance CEQM (pF)
CEQM
4.0
Input Buffer
Number of input buffers switching at fn
n1
Average input switching rate fn (MHz)
(Guidelines: f/5)
fn
40
Input buffer capacitance CEQI (pF)
CEQI
3.4
Output Buffer
Number of output buffers switching at fp p1
Average output buffers switching rate
fp(MHz) (Guidelines: f/10)
fp
20
Output buffers buffer capacitance
CEQO (pF)
CEQO
4.7
Output Load capacitance CL (pF)
CL
35
RCLKA
Number of Clock loads q1
q1
528
Capacitance of routed array clock (pF)
CEQCR 1.6
Average clock rate (MHz)
fq1
200
Fixed capacitance (pF)
r1
138
RCLKB
Number of Clock loads q2
q2
0
Capacitance of routed array clock (pF)
CEQCR 1.6
Average clock rate (MHz)
fq2
0
Fixed capacitance (pF)
r2
138
HCLK
Number of Clock loads
s1
0
Variable capacitance of dedicated
array clock (pF)
CEQHV 0.61
5
Fixed capacitance of dedicated
array clock (pF)
CEQHF 96
Average clock rate (MHz)
fs1
0
Step 2:
Calculate Dynamic Power Consumption
VCCA × VCCA
10.89
m × fm × CEQM
0.02112
n × fn × CEQI
0.000136
p × fp × (CEQO+CL)
0.000794
0.5 (q1 × CEQCR × fq1) + (r1 × fq1)
0.11208
0.5(q2 × CEQCR × fq2) + (r2 × fq2)0
0.5 (s1 × CEQHV × fs1) + (CEQHF × fs1)0
PAC = 1.461 W
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