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參數(shù)資料
| 型號： | A54SX32-1TQ208M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad 2-input positive-NOR gates 14-PDIP 0 to 70 |
| 中文描述： | 54SX家庭的FPGA |
| 文件頁數(shù)： | 12/57頁 |
| 文件大?。?/td> | 415K |
| 代理商： | A54SX32-1TQ208M |
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5 4 S X F a m ily F P G A s
12
v3.1
A 54S X 16P A C S pe c ific a tions for (P C I Ope ra tion)
Symbol
Parameter
Condition
0 < V
OUT
≤
1.4
1
1.4
≤
V
OUT
< 2.4
1, 2
Min.
Max.
Units
I
OH(AC)
Switching Current High
–44
mA
mA
–44 + (V
OUT
– 1.4)/0.024
3.1 < V
OUT
< V
CC1, 3
Equation A: on
page 13
–142
(Test Point)
V
OUT
= 3.1
3
V
OUT
≥
2.2
1
2.2 > V
OUT
> 0.55
1
mA
mA
I
OL(AC)
Switching Current High
95
V
OUT
/0.023
0.71 > V
OUT
> 0
1, 3
Equation B: on
page 13
206
mA
(Test Point)
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
V
OUT
= 0.71
3
–5 < V
IN
≤
–1
0.4V to 2.4V load
4
2.4V to 0.4V load
4
mA
mA
V/ns
V/ns
I
CL
slew
R
slew
F
Notes:
1.
–25 + (V
IN
+ 1)/0.015
1
1
5
5
Refer to the V/I curves in
Figure8
. Switching current characteristics for REQ#and GNT#are permitted to be one half of that specified here;
i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#which are system outputs.
“Switching Current High” specification are not relevant to SERR# INTA# INTB# INTC# and INTD#which are open drain outputs.
Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward
the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)
are provided with the respective diagrams in
Figure8
. The equation defined maxima should be met by design. In order to facilitate
component testing, a maximum current test point is defined for each side of the output driver.
This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is
now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to
revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard
designers must bear in mind that rise and fall times faster than this specification could occur, and should ensure that signal integrity
modeling accounts for this. Rise slew rate does not apply to open drain outputs.
2.
3.
4.
output
buffer
1/2 in. max.
V
CC
1k
10 pF
1k
pin
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| A54SX32-1TQ208PP | 54SX Family FPGAs |
| A54SX32-1VQ208PP | Quad 2-input positive-NOR gates 14-PDIP 0 to 70 |
| A54SX32-2BG208M | Quad 2-input positive-NOR gates 14-SO 0 to 70 |
| A54SX08P-PL208I | LM1877 Dual Audio Power Amplifier; Package: SOIC WIDE; No of Pins: 14; Qty per Container: 50; Container: Rail |
| A54SX08P-PL208M | 54SX Family FPGAs |
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