External Setup = tINY + t
參數(shù)資料
型號: A54SX32-2BG329I
廠商: Microsemi SoC
文件頁數(shù): 18/64頁
文件大小: 0K
描述: IC FPGA SX 48K GATES 329-BGA
標準包裝: 27
系列: SX
LAB/CLB數(shù): 2880
輸入/輸出數(shù): 249
門數(shù): 48000
電源電壓: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 329-BBGA
供應商設(shè)備封裝: 329-PBGA(31x31)
SX Family FPGAs
v3.2
1-21
SX Timing Model
Hardwired Clock
External Setup = tINY + tIRD1 + tSUD – tHCKH
= 1.5 + 0.3 + 0.5 – 1.0 = 1.3 ns
EQ 1-15
Clock-to-Out (Pin-to-Pin)
=tHCKH + tRCO + tRD1 + tDHL
= 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns
EQ 1-16
Routed Clock
External Setup = tINY + tIRD1 + tSUD – tRCKH
= 1.5 + 0.3 + 0.5 – 1.5 = 0.8 ns
EQ 1-17
Clock-to-Out (Pin-to-Pin)
=tRCKH + tRCO + tRD1 + tDHL
= 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns
EQ 1-18
Note: Values shown for A54SX08-3, worst-case commercial conditions.
Figure 1-12 SX Timing Model
DQ
Routed
Clock
F
MAX = 250 MHz
t
RCKH = 1.5 ns (100% Load)
t
INY = 1.5 ns
Output Delays
Input Delays
I/O Module
Combinatorial Cell
Register Cell
I/O Module
Hardwired
Clock
DQ
Predicted
Routing
Delays
t
IRD2 = 0.6 ns
t
PD = 0.6 ns
t
RD1 = 0.3 ns
t
RD4 = 1.0 ns
t
RD8 = 1.9 ns
t
DLH = 1.6 ns
t
DHL = 1.6 ns
F
HMAX = 320 MHz
t
HCKH = 1.0 ns
t
RCO = 0.8 ns
t
RD1 = 0.3 ns
t
ENZH = 2.3 ns
Internal Delays
t
RD1 = 0.3 ns
t
SUD = 0.5 ns
t
HD = 0.0 ns
Register Cell
t
RCO = 0.8 ns
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