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參數(shù)資料
| 型號： | A54SX32-3BG313 |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 833K |
| 代理商： | A54SX32-3BG313 |
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54SX Family FPGAs RadTolerant and HiRel
8
v2.0
Clock Resources
Actel
’
s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from the
HCLK buffer to the clock select MUX in each R-cell. HCLK
cannot be connected to combinational logic. This provides a
fast propagation path for the clock signal, enabling the
5.8 ns
clock-to-out (pad-to-pad) performance of the RT54SX devices.
The hard-wired clock is tuned to provide clock skew is less
than 0.5ns worst case.
The remaining two clocks (CLKA, CLKB) are global clocks
that can be sourced from external pins or from internal logic
signals within the RT54SX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals then the
external clock pin cannot be used for any other input and
must be tied low or high.
Figure8
describes the clock circuit
used for the constant load HCLK.
Figure 9
describes the
CLKA and CLKB circuit used in RT54SX devices with the
exception of RT54SX72S.
Other Architecture Features
Performance
The combination of architectural features described above
enables RT54SX devices to operate with internal clock
frequencies exceeding 160 MHz, enabling very fast
execution of complex logic functions. Thus, the RT54SX
family is an optimal platform upon which to integrate the
functionality previously contained in multiple CPLDs. In
addition, designs that previously would have required a gate
array to meet performance goals can now be integrated into
an RT54SX device with dramatic improvements in cost and
time-to-market. Using timing-driven place-and-route tools,
designers can achieve highly deterministic device
performance. With RT54SX devices, designers do not need
to
use
complicated
performance-enhancing
techniques such as redundant logic to reduce fanout on
critical nets or the instantiation of macros in HDL code to
achieve high performance.
design
I/O Modules
Each I/O on an RT54SX device can be configured as an
input, an output, a tristate output, or a bidirectional pin.
Even without the inclusion of dedicated registers, these
I/Os, in combination with array registers, can achieve
clock-to-out (PAD-to-PAD) timing as fast as 5.8 ns. I/O cells
including embedded latches and flip-flops require
instantiation in HDL code. This is a design complication not
encountered in RT54SX FPGAs. Fast PAD-to-PAD timing
ensures that the device will have little trouble interfacing
with any other device in the system, which in turn enables
parallel design of system components and reduces overall
design time.
Power Requirements
The RT54SX family supports either 3.3V or 5.0V I/O voltage
operation and is designed to tolerate 5V inputs in each case
(
Table 1
). Power consumption is extremely low due to the
very short distances signals are required to travel to
complete a circuit. Power requirements are further reduced
due to the small number of antifuses in the path, and
because of the low resistance properties of the antifuses.
The antifuse architecture does not require active circuitry
to hold a charge (as do SRAM or EPROM), making it the
lowest-power architecture on the market.
Table 1
Supply Voltages
Figure 8
RT54SX Constant Load Clock Pad
Figure 9
RT54SX Clock Pads
Constant Load
Clock Network
HCLKBUF
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
V
CCA
V
CCI
V
CCR
Maximum
Input
Tolerance
Maximum
Output
Drive
A54SX16
A54SX32
RTSX16
RTSX32
3.3V
3.3V
5.0V
3.3V
3.3V
3.3V
3.3V
5.0V
5.0V
3.3V
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