參數(shù)資料
型號： A54SX32-3VQ208I
廠商： Electronic Theatre Controls, Inc.
英文描述： LM2576/LM2576HV Series SIMPLE SWITCHER® 3A Step-Down Voltage Regulator; Package: TO-220; No of Pins: 5; Qty per Container: 45; Container: Rail
中文描述： 54SX家庭的FPGA
文件頁數(shù)： 32/57頁
文件大?。?/td> 415K
代理商： A54SX32-3VQ208I
5 4 S X F a m ily F P G A s
32
v3.1
A 5 4 S X 3 2 T im ing C ha ra c t e ris t ic s
(Wors t-C a s e C omme rc ia l C onditions , V
C C R
= 4.75 V , V
C C A ,
V
C C I
= 3.0V , T
J
= 70
°
C )
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
C-Cell Propagation Delays
1
t
PD
Predicted Routing Delays
2
Internal Array Module
0.6
0.7
0.8
0.9
ns
t
DC
t
FC
t
RD1
t
RD2
t
RD3
t
RD4
t
RD8
t
RD12
FO=1 Routing Delay, Direct Connect
0.1
0.1
0.1
0.1
ns
FO=1 Routing Delay, Fast Connect
0.3
0.4
0.4
0.5
ns
FO=1 Routing Delay
0.3
0.4
0.4
0.5
ns
FO=2 Routing Delay
0.7
0.8
0.9
1.0
ns
FO=3 Routing Delay
1.0
1.2
1.4
1.6
ns
FO=4 Routing Delay
1.4
1.6
1.8
2.1
ns
FO=8 Routing Delay
2.7
3.1
3.5
4.1
ns
FO=12 Routing Delay
4.0
4.7
5.3
6.2
ns
R-Cell Timing
t
RCO
t
CLR
t
PRESET
t
SUD
t
HD
t
WASYN
Sequential Clock-to-Q
0.8
1.1
1.3
1.4
ns
Asynchronous Clear-to-Q
0.5
0.6
0.7
0.8
ns
Asynchronous Preset-to-Q
0.7
0.8
0.9
1.0
ns
Flip-Flop Data Input Set-Up
0.5
0.6
0.7
0.8
ns
Flip-Flop Data Input Hold
0.0
0.0
0.0
0.0
ns
Asynchronous Pulse Width
1.4
1.6
1.8
2.1
ns
Input Module Propagation Delays
t
INYH
t
INYL
Predicted Input Routing Delays
2
Input Data Pad-to-Y HIGH
1.5
1.7
1.9
2.2
ns
Input Data Pad-to-Y LOW
1.5
1.7
1.9
2.2
ns
t
IRD1
t
IRD2
t
IRD3
t
IRD4
t
IRD8
t
IRD12
Notes:
1.
2.
FO=1 Routing Delay
0.3
0.4
0.4
0.5
ns
FO=2 Routing Delay
0.7
0.8
0.9
1.0
ns
FO=3 Routing Delay
1.0
1.2
1.4
1.6
ns
FO=4 Routing Delay
1.4
1.6
1.8
2.1
ns
FO=8 Routing Delay
2.7
3.1
3.5
4.1
ns
FO=12 Routing Delay
4.0
4.7
5.3
6.2
ns
For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
RD1
+ t
PDn
or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
相關(guān)PDF資料
PDF描述
A54SX32-3VQ208M LM2576/LM2576HV Series SIMPLE SWITCHER® 3A Step-Down Voltage Regulator; Package: TO-220; No of Pins: 5; Qty per Container: 45; Container: Rail
A54SX32-3VQ208PP LM2576/LM2576HV Series SIMPLE SWITCHER® 3A Step-Down Voltage Regulator; Package: TO-220; No of Pins: 5; Qty per Container: 45; Container: Rail
A54SX32-BG208 LM2576/LM2576HV Series SIMPLE SWITCHER® 3A Step-Down Voltage Regulator; Package: TO-220; No of Pins: 5; Qty per Container: 45; Container: Rail
A54SX32-BG208I LM2576/LM2576HV Series SIMPLE SWITCHER® 3A Step-Down Voltage Regulator; Package: TO-263; No of Pins: 5; Qty per Container: 45; Container: Rail
A54SX32-BG208M LM2576/LM2576HV Series SIMPLE SWITCHER® 3A Step-Down Voltage Regulator; Package: TO-263; No of Pins: 5; Qty per Container: 45; Container: Rail
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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