參數(shù)資料
型號(hào)： A54SX32-BG313M
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 833K
代理商： A54SX32-BG313M
v2.0
9
54SX Family FPGAs RadTolerant and HiRel
Boundary Scan Testing (BST)
All RT54SX devices are IEEE 1149.1 (JTAG) compliant.
They offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing
capabilities. These functions are controlled through the
special test pins in conjunction with the program fuse. The
functionality of each pin is described in
Table 2
.
Figure 10
is a block diagram of the RT54SX JTAG circuitry.
Configuring Diagnostic Pins
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the
“
Variation
”
dialog window.
This dialog window is accessible through the Design Setup
Wizard under the Tools menu in Actel
’
s Designer software.
TRST pin
The TRST pin functions as a Boundary Scan Reset pin. The
TRST pin is an asynchronous, active-low input to initialize
or reset the BST circuit. An internal pull-up resistor is
automatically enabled on the TRST pin.
Dedicated Test Mode
When the
“
Reserve JTAG
”
box is checked in the Designer
software, the RT54SX is placed in Dedicated Test mode, which
configures the TDI, TCK, and TDO pins for BST or in-circuit
verification with Silicon Explorer II. An internal pull-up resistor
is automatically enabled on both the TMS and TDI pins. In
dedicated test mode, TCK, TDI, and TDO are dedicated test pins
and become unavailable for pin assignment in the Pin Editor.
The TMS pin will function as specified in the IEEE 1149.1
(JTAG) Specification.
Flexible Mode
When the
“
Reserve JTAG
”
box is not selected (default setting
in Designer software), the RT54SX is placed in flexible mode,
which allows the TDI, TCK, and TDO pins to function as user
I/Os or BST pins. In this mode the internal pull-up resistors on
the TMS and TDI pins are disabled. An external 10k
pull-up
resistor to VCCI is required on the TMS pin.
The TDI, TCK, and TDO pins are transformed from user I/Os
into BST pins when a rising edge on TCK is detected while
TMS is at logical low. Once the BST pins are in test mode
they will remain in BST mode until the internal BST state
Table 2
Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated test pins
No need for pull-up resistor
for TMS
TCK, TDI, TDO are flexible
and may be used as I/Os
Use a pull-up resistor of
10k
on TMS
Figure 10
RT54SX JTAG Circuitry
Instruction Register (IR)
Data Registers (DRs)
clocks and/or controls
TAP Controller
output
stage
0
1
TDO
TDI
TMS
TCK
TRST external
hard-wired pin
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