參數(shù)資料
型號(hào): A54SX32A-1CQ208C
元件分類: FPGA
英文描述: FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP208
封裝: CERAMIC, QFP-208
文件頁(yè)數(shù): 20/40頁(yè)
文件大小: 738K
代理商: A54SX32A-1CQ208C
27
Hi R e l S X -A F a m i l y F P G A s
A5 4S X72 A Ti m i ng Ch ar ac te r i s t i c s (Continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s V CCA = 2. 3V , V CCI = 3 .0V , TJ = 12 5°C)
Dedicated (Hardwired) Array Clock Network
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
2.4
2.9
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
2.1
2.6
ns
tHPWH
Minimum Pulse Width HIGH
2.1
2.4
ns
tHPWL
Minimum Pulse Width LOW
2.1
2.4
ns
tHCKSW
Maximum Skew
0.5
0.6
ns
tHP
Minimum Period
4.2
4.9
ns
fHMAX
Maximum Frequency
241
206
MHz
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
4.2
4.9
ns
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
4.4
5.2
ns
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
5.1
6.0
ns
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
5.2
6.2
ns
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
7.0
8.1
ns
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
7.0
8.2
ns
tRPWH
Min. Pulse Width HIGH
3.1
3.7
ns
tRPWL
Min. Pulse Width LOW
3.1
3.7
ns
tRCKSW
Maximum Skew (Light Load)
1.3
1.5
ns
tRCKSW
Maximum Skew (50% Load)
1.9
2.2
ns
tRCKSW
Maximum Skew (100% Load)
2.0
2.3
ns
Quadrant Clock Networks
tQCKH
Input LOW to HIGH (Light Load)
2.3
2.7
ns
tQCKL
Input HIGH to LOW (Light Load)
2.6
3.1
ns
tQCKH
Input LOW to HIGH (50% Load)
2.4
2.8
ns
tQCKL
Input HIGH to LOW (50% Load)
2.7
3.2
ns
tQCKH
Input LOW to HIGH (100% Load)
2.6
3.0
ns
tQCKL
Input HIGH to LOW (100% Load)
2.9
3.4
ns
tQCKSW
Maximum Skew (Light Load)
0.3
0.4
ns
tQCKSW
Maximum Skew (50% Load)
0.4
0.5
ns
tQCKSW
Maximum Skew (100% Load)
0.5
0.6
ns
相關(guān)PDF資料
PDF描述
A54SX32A-1CQ256C FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP256
A54SX32A-1CQG208C FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP208
A54SX32A-1CQG256C FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP256
A54SX32A-CQ208C FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208
A54SX32A-CQ256C FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP256
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