Table 2-5 3.3 V LVTTL and 5 V TTL Electrical Specifications Symbol Parameter Commercial " />
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  • 參數(shù)資料
    型號: A54SX32A-1CQ256
    廠商: Microsemi SoC
    文件頁數(shù): 24/108頁
    文件大?。?/td> 0K
    描述: IC FPGA SX 48K GATES 256-CQFP
    標(biāo)準(zhǔn)包裝: 1
    系列: SX-A
    LAB/CLB數(shù): 2880
    輸入/輸出數(shù): 203
    門數(shù): 48000
    電源電壓: 2.25 V ~ 5.25 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 256-BFCQFP,帶拉桿
    供應(yīng)商設(shè)備封裝: 256-CQFP(75x75)
    SX-A Family FPGAs
    2- 2
    v5.3
    Electrical Specifications
    Table 2-5 3.3 V LVTTL and 5 V TTL Electrical Specifications
    Symbol
    Parameter
    Commercial
    Industrial
    Min.
    Max.
    Min.
    Max.
    Units
    VOH
    VCCI = Minimum
    VI = VIH or VIL
    (IOH = –1 mA)
    0.9 VCCI
    V
    VCCI = Minimum
    VI = VIH or VIL
    (IOH = –8 mA)
    2.4
    V
    VOL
    VCCI = Minimum
    VI = VIH or VIL
    (IOL= 1 mA)
    0.4
    V
    VCCI = Minimum
    VI = VIH or VIL
    (IOL= 12 mA)
    0.4
    V
    VIL
    Input Low Voltage
    0.8
    V
    VIH
    Input High Voltage
    2.0
    5.75
    2.0
    5.75
    V
    IIL/IIH
    Input Leakage Current, VIN = VCCI or GND
    –10
    10
    –10
    10
    A
    IOZ
    Tristate Output Leakage Current
    –10
    10
    –10
    10
    A
    tR, tF
    Input Transition Time tR, tF
    10
    ns
    CIO
    I/O Capacitance
    10
    pF
    ICC
    Standby Current
    10
    20
    mA
    IV Curve* Can be derived from the IBIS model on the web.
    Note: *The IBIS model can be found at http://www.actel.com/download/ibis/default.aspx.
    Table 2-6 2.5 V LVCMOS2 Electrical Specifications
    Symbol
    Parameter
    Commercial
    Industrial
    Min.
    Max.
    Min.
    Max.
    Units
    VOH
    VDD = MIN,
    VI = VIH or VIL
    (IOH = –100 μA)
    2.1
    V
    VDD = MIN,
    VI = VIH or VIL
    (IOH = –1 mA)
    2.0
    V
    VDD = MIN,
    VI = VIH or VIL
    (IOH =–-2 mA)
    1.7
    VOL
    VDD = MIN,
    VI = VIH or VIL
    (IOL= 100 μA)
    0.2
    V
    VDD = MIN,
    VI = VIH or VIL
    (IOL= 1 mA)
    0.4
    V
    VDD = MIN,
    VI = VIH or VIL
    (IOL= 2 mA)
    0.7
    V
    VIL
    Input Low Voltage, VOUT ≤ VVOL(max)
    -0.3
    0.7
    -0.3
    0.7
    V
    VIH
    Input High Voltage, VOUT ≥ VVOH(min)
    1.75.751.7
    5.75
    V
    IIL/IIH
    Input Leakage Current, VIN = VCCI or GND
    –10
    10
    –10
    10
    A
    IOZ
    Tristate Output Leakage Current, VOUT = VCCI or GND
    –10
    10
    –10
    10
    A
    tR, tF
    Input Transition Time tR, tF
    10
    ns
    CIO
    I/O Capacitance
    10
    pF
    ICC
    Standby Current
    10
    20
    mA
    IV Curve* Can be derived from the IBIS model on the web.
    Note: *The IBIS model can be found at http://www.actel.com/download/ibis/default.aspx.
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