參數(shù)資料
型號(hào)： A54SX32A-1FG484
廠商： Microsemi SoC
文件頁(yè)數(shù)： 14/108頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SX 48K GATES 484-FBGA
標(biāo)準(zhǔn)包裝： 40
系列： SX-A
LAB/CLB數(shù)： 2880
輸入/輸出數(shù)： 249
門數(shù)： 48000
電源電壓： 2.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（27X27）
SX-A Family FPGAs
v5.3
1-9
Boundary-Scan Testing (BST)
All SX-A devices are IEEE 1149.1 compliant and offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
The BST function is controlled through the special JTAG
pins (TMS, TDI, TCK, TDO, and TRST). The functionality of
the JTAG pins is defined by two available modes:
Dedicated and Flexible. TMS cannot be employed as a
user I/O in either mode.
Dedicated Mode
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, the user must reserve the
JTAG pins in Actel’s Designer software. Reserve the JTAG
pins by checking the Reserve JTAG box in the Device
Selection Wizard (Figure 1-12).
The default for the software is Flexible mode; all boxes
are unchecked. Table 1-5 lists the definitions of the
options in the Device Selection Wizard.
Flexible Mode
In Flexible mode, TDI, TCK, and TDO may be employed as
either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are not present in
flexible JTAG mode.
To select the Flexible mode, uncheck the Reserve JTAG
box in the Device Selection Wizard dialog in the Actel
Designer software. In Flexible mode, TDI, TCK, and TDO
pins may function as user I/Os or BST pins. The
functionality is controlled by the BST Test Access Port
(TAP) controller. The TAP controller receives two control
inputs, TMS and TCK. Upon power-up, the TAP controller
enters the Test-Logic-Reset state. In this state, TDI, TCK,
and TDO function as user I/Os. The TDI, TCK, and TDO are
transformed from user I/Os into BST pins when a rising
edge on TCK is detected while TMS is at logic low. To
return to Test-Logic Reset state, TMS must be high for at
least five TCK cycles. An external 10 k pull-up resistor
to VCCI should be placed on the TMS pin to pull it
High by default.
describes
the
different
configuration
requirements of BST pins and their functionality in
different modes.
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan
Reset pin when the Reserve JTAG Test Reset option is
selected as shown in Figure 1-12. An internal pull-up
resistor is permanently enabled on the TRST pin in this
mode. Actel recommends connecting this pin to ground
in normal operation to keep the JTAG state controller in
the Test-Logic-Reset state. When JTAG is being used, it
can be left floating or can be driven high.
When the Reserve JTAG Test Reset option is not
selected, this pin will function as a regular I/O. If unused
as an I/O in the design, it will be configured as a tristated
output.
Figure 1-12 Device Selection Wizard
Table 1-5 Reserve Pin Definitions
Pin
Function
Reserve JTAG
Keeps pins from being used and
changes the behavior of JTAG pins (no
pull-up on TMS)
Reserve
JTAG
Test
Reset
Regular I/O or JTAG reset with an
internal pull-up
Reserve Probe
Keeps pins from being used or regular
I/O
Table 1-6 Boundary-Scan Pin Configurations and
Functions
Mode
Designer
"Reserve JTAG"
Selection
TAP Controller
State
Dedicated (JTAG)
Checked
Any
Flexible (User I/O)
Unchecked
Test-Logic-Reset
Flexible (JTAG)
Unchecked
Any EXCEPT Test-
Logic-Reset
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參數(shù)描述
A54SX32A-1FG484I 功能描述:IC FPGA SX 48K GATES 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A54SX32A-1FG484M 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 484 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 48K GATES 484FBGA 制造商:Microsemi Corporation 功能描述:IC FPGA 249 I/O 484FBGA
A54SX32A-1FGG144 功能描述:IC FPGA SX 48K GATES 144-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX32A-1FGG144I 功能描述:IC FPGA SX 48K GATES 144-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX32A-1FGG144M 制造商:Microsemi Corporation 功能描述:FPGA SX-A Family 32K Gates 1800 Cells 278MHz 0.25um Technology 2.5V 144-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 144 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 111 I/O 144FBGA 制造商:Microsemi Corporation 功能描述:IC FPGA 48K GATES 144FBGA
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