Note: *Values shown for A54SX72A, –2, worst-ca" />
參數(shù)資料
型號: A54SX32A-BG329I
廠商: Microsemi SoC
文件頁數(shù): 37/108頁
文件大小: 0K
描述: IC FPGA SX 48K GATES 329-BGA
標準包裝: 27
系列: SX-A
LAB/CLB數(shù): 2880
輸入/輸出數(shù): 249
門數(shù): 48000
電源電壓: 2.25 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 329-BBGA
供應(yīng)商設(shè)備封裝: 329-PBGA(31x31)
SX-A Family FPGAs
2- 14
v5.3
SX-A Timing Model
Sample Path Calculations
Hardwired Clock
Routed Clock
Note: *Values shown for A54SX72A, –2, worst-case commercial conditions at 5 V PCI with standard place-and-route.
Figure 2-3 SX-A Timing Model
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
t
INYH = 0.6 ns
t
RD2 = 0.5 ns
t
RD1 = 0.3 ns
Combinatorial
Cell
I/O Module
t
DHL = 3.9 ns
t
RD8 = 1.5 ns
t
RD4 = 0.9 ns
t
RD1 = 0.3 ns
t
PD = 1.1 ns
I/O Module
t
DHL = 3.9 ns
t
RD1 = 0.3 ns
t
RCO= 0.8 ns
I/O Module
t
INYH = 0.6 ns
t
ENZL= 1.5 ns
t
SUD = 0.8 ns
t
HD = 0.0 ns
t
SUD = 0.8 ns
t
HD = 0.0 ns
t
RCKH = 3.0 ns
(100% Load)
DQ
Register
Cell
Routed
Clock
t
RD1 = 0.3 ns
t
RCO= 0.8 ns
t
HCKH= 1.8 ns
DQ
Register
Cell
Hardwired
Clock
I/O Module
t
DHL = 3.9 ns
t
ENZL= 1.5 ns
External Setup
= (tINYH + tRD1 + tSUD) – tHCKH
= 0.6 + 0.3 + 0.8 - 1.8 = – 0.1 ns
Clock-to-Out (Pad-to-Pad) = tHCKH + tRCO + tRD1 + tDHL
= 1.8 + 0.8 + 0.3 + 3.9 = 6.8 ns
External Setup
= (tINYH + tRD1 + tSUD) – tRCKH
= 0.6 + 0.3 + 0.8 - 3.0 = –1.3 ns
Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tDHL
= 3.0 + 0.8 + 0.3 + 3.9 = 8.0 ns
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