Table 2-31 A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V
參數(shù)資料
型號: A54SX32A-FG484I
廠商: Microsemi SoC
文件頁數(shù): 63/108頁
文件大?。?/td> 0K
描述: IC FPGA SX 48K GATES 484-FBGA
標(biāo)準(zhǔn)包裝: 40
系列: SX-A
LAB/CLB數(shù): 2880
輸入/輸出數(shù): 249
門數(shù): 48000
電源電壓: 2.25 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(27X27)
SX-A Family FPGAs
2- 38
v5.3
Table 2-31 A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
Parameter
Description
–3 Speed*
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input Low to High
(Pad to R-cell Input)
1.7
1.9
2.2
2.6
4.0
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHPWH
Minimum Pulse Width High
1.4
1.6
1.8
2.1
2.9
ns
tHPWL
Minimum Pulse Width Low
1.4
1.6
1.8
2.1
2.9
ns
tHCKSW
Maximum Skew
0.6
0.7
0.8
1.3
ns
tHP
Minimum Period
2.8
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
357
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.5
2.8
3.3
4.7
ns
tRCKL
Input High to Low (Light Load)
(Pad to R-cell Input)
2.1
2.5
2.8
3.3
4.5
ns
tRCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
2.4
2.7
3.1
3.6
5.1
ns
tRCKL
Input High to Low (50% Load)
(Pad to R-cell Input)
2.2
2.6
2.9
3.4
4.7
ns
tRCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
2.5
2.8
3.2
3.8
5.3
ns
tRCKL
Input High to Low (100% Load)
(Pad to R-cell Input)
2.4
2.8
3.1
3.7
5.2
ns
tRPWH
Minimum Pulse Width High
1.4
1.6
1.8
2.1
2.9
ns
tRPWL
Minimum Pulse Width Low
1.4
1.6
1.8
2.1
2.9
ns
tRCKSW
Maximum Skew (Light Load)
1.0
1.1
1.3
1.5
2.1
ns
tRCKSW
Maximum Skew (50% Load)
1.0
1.1
1.3
1.5
2.1
ns
tRCKSW
Maximum Skew (100% Load)
1.0
1.1
1.3
1.5
2.1
ns
Note: *All –3 speed grades have been discontinued.
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