Table 2-41 A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V
參數(shù)資料
型號(hào): A54SX32A-TQ176
廠商: Microsemi SoC
文件頁數(shù): 79/108頁
文件大?。?/td> 0K
描述: IC FPGA SX 48K GATES 176-TQFP
標(biāo)準(zhǔn)包裝: 40
系列: SX-A
LAB/CLB數(shù): 2880
輸入/輸出數(shù): 147
門數(shù): 48000
電源電壓: 2.25 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 176-LQFP
供應(yīng)商設(shè)備封裝: 176-TQFP(24x24)
SX-A Family FPGAs
2- 52
v5.3
Table 2-41 A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
Parameter
Description
–3 Speed1
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
5 V PCI Output Module Timing2
tDLH
Data-to-Pad Low to High
2.7
3.1
3.5
4.1
5.7
ns
tDHL
Data-to-Pad High to Low
3.4
3.9
4.4
5.1
7.2
ns
tENZL
Enable-to-Pad, Z to L
1.3
1.5
1.7
2.0
2.8
ns
tENZH
Enable-to-Pad, Z to H
2.7
3.1
3.5
4.1
5.7
ns
tENLZ
Enable-to-Pad, L to Z
3.0
3.5
3.9
4.6
6.4
ns
tENHZ
Enable-to-Pad, H to Z
3.4
3.9
4.4
5.1
7.2
ns
dTLH
3
Delta Low to High
0.016
0.02
0.022
0.032
ns/pF
dTHL
3
Delta High to Low
0.026
0.03
0.032
0.04
0.052
ns/pF
5 V TTL Output Module Timing4
tDLH
Data-to-Pad Low to High
2.4
2.8
3.1
3.7
5.1
ns
tDHL
Data-to-Pad High to Low
3.1
3.5
4.0
4.7
6.6
ns
tDHLS
Data-to-Pad High to Low—low slew
7.4
8.5
9.7
11.4
15.9
ns
tENZL
Enable-to-Pad, Z to L
2.1
2.4
2.7
3.2
4.5
ns
tENZLS
Enable-to-Pad, Z to L—low slew
7.4
8.4
9.5
11.0
15.4
ns
tENZH
Enable-to-Pad, Z to H
2.4
2.8
3.1
3.7
5.1
ns
tENLZ
Enable-to-Pad, L to Z
3.6
4.2
4.7
5.6
7.8
ns
tENHZ
Enable-to-Pad, H to Z
3.1
3.5
4.0
4.7
6.6
ns
dTLH
3
Delta Low to High
0.014
0.017
0.023
0.031
ns/pF
dTHL
3
Delta High to Low
0.023
0.029
0.031
0.037
0.051
ns/pF
dTHLS
3
Delta High to Low—low slew
0.043
0.046
0.057
0.066
0.089
ns/pF
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 50 pF loading.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])
where Cload is the load capacitance driven by the I/O in pF
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
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