參數(shù)資料
型號(hào)： A54SX32P-1TQ208I
廠商： Electronic Theatre Controls, Inc.
英文描述： LM2590HV SIMPLE SWITCHERPower Converter 150 kHz 1A Step-Down Voltage Regulator, with Features; Package: TO-220; No of Pins: 7; Qty per Container: 45; Container: Rail
中文描述： 54SX家庭的FPGA
文件頁(yè)數(shù)： 19/57頁(yè)
文件大?。?/td> 415K
代理商： A54SX32P-1TQ208I
v3.1
19
5 4 S X F a m ily F P G A s
G uide line s for C a lc ula t ing P ow e r
C ons um pt ion
The following guidelines are meant to represent worst-case
scenarios so that they can be generally used to predict the
upper limits of power dissipation. These guidelines are as
follow:
Logic Modules (m)
Inputs Switching (n)
Outputs Switching (p)
First Routed Array Clock Loads (q
1
)
S a m ple P ow e r C a lc ula t ion
One of the designs used to characterize the A54SX family
was a 528 bit serial in serial out shift register. The design
utilized 100%of the dedicated flip-flops of an A54SX16P
device. A pattern of 0101… was clocked into the device at
frequencies ranging from 1 MHz to 200 MHz. Shifting in a
series of 0101… caused 50%of the flip-flops to toggle from
low to high at every clock cycle.
Follow the steps below to estimate power consumption. The
values provided for the sample calculation below are for the
shift register design above. This method for estimating
power consumption is conservative and the actual power
consumption of your design may be less than the estimated
power consumption.
The total power dissipation for the 54SX family is the sum of
the AC power dissipation and the DC power dissipation.
P
Total
= P
AC
(dynamic power) + P
DC
(static power)
(5)
A C P ow e r Dis s ipa t ion
P
AC
= P
Module
+ P
RCLKA Net
+ P
RCLKB Net
+ P
HCLK Net
+
P
Output Buffer
+ P
Input Buffer
P
AC
= V
CCA2
* [(m * C
EQM
* f
m
)
Module
+
(n * C
EQI
* f
n
)
Input Buffer
+ (p * (C
EQO
+ C
L
) * f
p
)
Output
Buffer
+
(0.5 * (q
1
* C
EQCR
* f
q1
) + (r
1
* f
q1
))
RCLKA
+
(0.5 * (q
2
* C
EQCR
* f
q2
)+ (r
2
* f
q2
))
RCLKB
+
(0.5 * (s
1
* C
EQHV
* f
s1
) + (C
EQHF
* f
s1
))
HCLK
]
Step #1:
Define Terms Used in Formula
V
CCA
Module
Number of logic modules switching at f
m
(Used 50%
Average logic modules switching rate
f
m
(MHz) (Guidelines: f/10)
Module capacitance C
EQM
(pF)
Input Buffer
Number of input buffers switching at f
n
Average input switching rate f
n
(MHz)
(Guidelines: f/5)
Input buffer capacitance C
EQI
(pF)
Output Buffer
Number of output buffers switching at f
p
Average output buffers switching rate
f
p
(MHz) (Guidelines: f/10)
Output buffers buffer Capacitance C
EQO
(pF) C
EQO
4.7
Output Load capacitance C
L
(pF)
RCLKA
Number of Clock loads q
1
Capacitance of routed array clock (pF)
Average clock rate (MHz)
Fixed capacitance (pF)
RCLKB
Number of Clock loads q
2
Capacitance of routed array clock (pF)
Average clock rate (MHz)
Fixed capacitance (pF)
HCLK
Number of Clock loads
Variable capacitance of dedicated
array clock (pF)
Fixed capacitance of dedicated
array clock (pF)
Average clock rate (MHz)
(6)
(7)
= 20%of modules
= #inputs/4
= #output/4
= 20%of register
cells
Second Routed Array Clock Loads (q
2
) = 20%of register
cells
Load Capacitance (C
L
)
Average Logic Module Switching Rate
(f
m
)
Average Input Switching Rate (f
n
)
Average Output Switching Rate (f
p
)
Average First Routed Array Clock Rate
(f
q1
)
Average Second Routed Array Clock
Rate (f
q2
)
Average Dedicated Array Clock Rate
(f
s1
)
Dedicated Clock Array clock loads (s
1
) = 20%of regular
= 35 pF
= f/10
= f/5
= f/10
= f/2
= f/2
= f
modules
3.3
m
264
f
m
20
C
EQM
4.0
n
f
n
1
40
C
EQI
3.4
p
f
p
1
20
C
L
35
q
1
C
EQCR
1.6
f
q1
r
1
528
200
138
q
2
C
EQCR
1.6
f
q2
r
2
0
0
138
s
1
C
EQHV
0.615
0
C
EQHF
96
f
s1
0
相關(guān)PDF資料
PDF描述
A54SX32P-1TQ208M LM2590HV SIMPLE SWITCHERPower Converter 150 kHz 1A Step-Down Voltage Regulator, with Features; Package: TO-220; No of Pins: 7; Qty per Container: 45; Container: Rail
A54SX32P-1TQ208PP 54SX Family FPGAs
A54SX32P-1VQ208PP 54SX Family FPGAs
A54SX32P-2BG208M 54SX Family FPGAs
A54SX32P-2FG208M LM2591HV SIMPLE SWITCHERPower Converter 150 kHz 1A Step-Down Voltage Regulator; Package: TO-263; No of Pins: 5; Qty per Container: 45; Container: Rail
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A54SX32-PQ208 功能描述:IC FPGA SX 48K GATES 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A54SX32-PQ208I 功能描述:IC FPGA SX 48K GATES 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A54SX32-PQ208M 功能描述:IC FPGA SX 48K GATES 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A54SX32-PQG208 功能描述:IC FPGA SX 48K GATES 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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