參數(shù)資料
| 型號： | A54SX72A-1PQ208 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 98/108頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA SX-A 108K 208-PQFP |
| 標準包裝： | 24 |
| 系列： | SX-A |
| LAB/CLB數(shù)： | 6036 |
| 輸入/輸出數(shù)： | 171 |
| 門數(shù)： | 108000 |
| 電源電壓： | 2.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
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SX-A Family FPGAs
v5.3
1-5
Clock Resources
Actel’s high-drive routing structure provides three clock
networks (Table 1-1). The first clock, called HCLK, is
hardwired from the HCLK buffer to the clock select
multiplexor (MUX) in each R-cell. HCLK cannot be
connected to combinatorial logic. This provides a fast
propagation path for the clock signal. If not used, this
pin must be set as Low or High on the board. It must not
be left floating. Figure 1-7 describes the clock circuit
used for the constant load HCLK and the macros
supported.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Design
software and the pin must be tied to GND on the board.
Two additional clocks (CLKA, CLKB) are global clocks that
can be sourced from external pins or from internal logic
signals within the SX-A device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB pins are not used or sourced from signals,
these pins must be set as Low or High on the board. They
must not be left floating. Figure 1-8 describes the CLKA
and CLKB circuit used and the macros supported in SX-A
devices with the exception of A54SX72A.
In
addition,
the
A54SX72A
device
provides
four
quadrant clocks (QCLKA, QCLKB, QCLKC, and QCLKD—
corresponding to bottom-left, bottom-right, top-left,
and top-right locations on the die, respectively), which
can be sourced from external pins or from internal logic
signals within the device. Each of these clocks can
individually drive up to an entire quadrant of the chip,
or they can be grouped together to drive multiple
quadrants (Figure 1-9 on page 1-6). QCLK pins can
function as user I/O pins. If not used, the QCLK pins
must be tied Low or High on the board and must not be
left floating.
For more information on how to use quadrant clocks in
the A54SX72A device, refer to the Global Clock Networks
RT54SX72S Quadrant Clocks application notes.
The CLKA, CLKB, and QCLK circuits for A54SX72A as well
as the macros supported are shown in Figure 1-10 on
page 1-6. Note that bidirectional clock buffers are only
available in A54SX72A. For more information, refer to
Table 1-1 SX-A Clock Resources
A54SX08A
A54SX16A
A54SX32A
A54SX72A
Routed Clocks (CLKA, CLKB)
2
Hardwired Clocks (HCLK)
1
Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD)
0
4
Figure 1-7 SX-A HCLK Clock Buffer
Figure 1-8 SX-A Routed Clock Buffer
Constant Load
Clock Network
HCLKBUF
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
相關PDF資料 |
PDF描述 |
|---|---|
| A54SX72A-PQG208I | IC FPGA SX-A 108K 208-PQFP |
| A54SX72A-PQ208I | IC FPGA SX-A 108K 208-PQFP |
| A54SX72A-1PQG208 | IC FPGA SX-A 108K 208-PQFP |
| AMC31DRXN | CONN EDGECARD 62POS .100 DIP SLD |
| AMC31DRXH | CONN EDGECARD 62POS .100 DIP SLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX72A-1PQ208I | 功能描述:IC FPGA SX-A 108K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
| A54SX72A-1PQ208IX174 | 制造商:Microsemi Corporation 功能描述:SX-A 72K GATES 4024 MC 250MHZ IND ANTIFUSE 2.5/3.3/5V 208QFP - Trays |
| A54SX72A-1PQ208M | 制造商:Microsemi Corporation 功能描述:FPGA SX-A 72K GATES 4024 CELLS 250MHZ 0.25UM/0.22UM 2.5V 208 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 171 I/O 208PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 108K GATES 208PQFP |
| A54SX72A-1PQG208 | 功能描述:IC FPGA SX-A 108K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
| A54SX72A-1PQG208I | 功能描述:IC FPGA SX-A 108K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
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