Table 2-32 A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V
參數(shù)資料
型號(hào): A54SX72A-FGG256I
廠商: Microsemi SoC
文件頁數(shù): 64/108頁
文件大小: 0K
描述: IC FPGA SX-A 108K 256-FBGA
標(biāo)準(zhǔn)包裝: 90
系列: SX-A
LAB/CLB數(shù): 6036
輸入/輸出數(shù): 203
門數(shù): 108000
電源電壓: 2.25 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
SX-A Family FPGAs
v5.3
2-39
Table 2-32 A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3 V, TJ = 70°C)
Parameter
Description
–3 Speed1
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2.5 V LVCMOS Output Module Timing 2,3
tDLH
Data-to-Pad Low to High
3.3
3.8
4.2
5.0
7.0
ns
tDHL
Data-to-Pad High to Low
2.5
2.9
3.2
3.8
5.3
ns
tDHLS
Data-to-Pad High to Low—low slew
11.1
12.8
14.5
17.0
23.8
ns
tENZL
Enable-to-Pad, Z to L
2.4
2.8
3.2
3.7
5.2
ns
tENZLS
Data-to-Pad, Z to L—low slew
11.8
13.7
15.5
18.2
25.5
ns
tENZH
Enable-to-Pad, Z to H
3.3
3.8
4.2
5.0
7.0
ns
tENLZ
Enable-to-Pad, L to Z
2.1
2.5
2.8
3.3
4.7
ns
tENHZ
Enable-to-Pad, H to Z
2.5
2.9
3.2
3.8
5.3
ns
dTLH
4
Delta Low to High
0.031
0.037
0.043
0.051
0.071
ns/pF
dTHL
4
Delta High to Low
0.017
0.023
0.037
ns/pF
dTHLS
4
Delta High to Low—low slew
0.057
0.06
0.071
0.086
0.117
ns/pF
Note:
1. All –3 speed grades have been discontinued.
2. Delays based on 35 pF loading.
3. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.
4. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])
where Cload is the load capacitance driven by the I/O in pF
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
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