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參數(shù)資料
| 型號(hào)： | A54SX72A-PQ208A |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 65/108頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA SX-A 108K 208-PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | SX-A |
| LAB/CLB數(shù)： | 6036 |
| 輸入/輸出數(shù)： | 171 |
| 門數(shù)： | 108000 |
| 電源電壓： | 2.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
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SX-A Family FPGAs
1- 2
v5.3
Logic Module Design
The SX-A family architecture is described as a “sea-of-
modules” architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. The Actel SX-A family provides two types of
logic
modules:
the
register
cell
(R-cell)
and
the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable, using the S0 and S1
lines control signals (Figure 1-2). The R-cell registers feature
programmable clock polarity selectable on a register-by-
register basis. This provides additional flexibility while
allowing mapping of synthesized functions into the SX-A
FPGA. The clock source for the R-cell can be chosen from
either the hardwired clock, the routed clocks, or internal
logic.
The C-cell implements a range of combinatorial functions
of up to five inputs (Figure 1-3). Inclusion of the DB input
and its associated inverter function allows up to 4,000
different combinatorial functions to be implemented in a
single module. An example of the flexibility enabled by
the inversion capability is the ability to integrate a 3-input
exclusive-OR function into a single C-cell. This facilitates
construction of 9-bit parity-tree functions with 1.9 ns
propagation delays.
Module Organization
All C-cell and R-cell logic modules are arranged into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
Clusters
are
grouped
together
into
SuperClusters
(Figure 1-4 on page 1-3). SuperCluster 1 is a two-wide
grouping of Type 1 Clusters. SuperCluster 2 is a two-wide
group containing one Type 1 Cluster and one Type 2
Cluster. SX-A devices feature more SuperCluster 1
modules than SuperCluster 2 modules because designers
typically require significantly more combinatorial logic
than flip-flops.
Figure 1-2 R-Cell
Figure 1-3 C-Cell
DQ
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLR
PRE
Y
Routed
Data Input
S0
S1
D0
D1
D2
D3
DB
A0 B0
A1 B1
Sa
Sb
Y
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX72A-PQ208I | 功能描述:IC FPGA SX-A 108K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A54SX72A-PQ208IX160 | 制造商:Microsemi Corporation 功能描述:FPGA SX-A 72K GATES 4024 CELLS 217MHZ 0.25UM/0.22UM 2.5V 208 - Trays |
| A54SX72A-PQ208IX3 | 制造商:Microsemi Corporation 功能描述:FPGA SX-A 72K GATES 4024 CELLS 217MHZ 0.25UM/0.22UM 2.5V 208 - Trays |
| A54SX72A-PQ208IX60 | 制造商:Microsemi Corporation 功能描述:FPGA SX-A 72K GATES 4024 CELLS 217MHZ 0.25UM/0.22UM 2.5V 208 - Trays |
| A54SX72A-PQ208M | 制造商:Microsemi Corporation 功能描述:FPGA SX-A Family 72K Gates 4024 Cells 217MHz 0.25um Technology 2.5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA SX-A Family 72K Gates 4024 Cells 217MHz 0.25um/0.22um (CMOS) Technology 2.5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA SX-A 72K GATES 4024 CELLS 217MHZ 0.25UM/0.22UM 2.5V 208 - Trays |
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