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參數(shù)資料
| 型號： | A7002AGHN1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | A700x family Secure authentication microcontroller |
| 文件頁數(shù)： | 13/19頁 |
| 文件大小： | 207K |
| 代理商： | A7002AGHN1 |
A700X_FAM_SDS
Preliminary short data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Rev. 2.0 — 25 August 2011
202020
13 of 19
NXP Semiconductors
A700x family
Secure authentication microcontroller
8. Limiting values
Table 8.
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
VSS (ground = 0 V).
Symbol Parameter
Conditions
V
DD
supply voltage
V
I
input voltage
any signal pad
I
I
input current
pad SDA, SCL or
IO3
I
O
output current
pad SDA, SCL or
IO3
I
lu
latch-up current
V
I
< 0 V
or V
I
> V
DD
V
ESD
electrostatic discharge voltage
pads VDD, VSS,
SDA, SCL, IO3
P
tot
total power dissipation
T
stg
storage temperature
[1]
MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 k
; T
amb
=
25
C to +85
C.
Depending on appropriate thermal resistance of the package.
[2]
[3]
Depending on delivery type, refer to
NXP Semiconductors General Specification for 8” Wafer
s and to
NXP
Semiconductors Contact & Dual Interface Chip Card Module Specification
.
9. Application information
Figure 4
shows a typical application diagram. It shows how the pins of the A700x family
shall be applied in order to operate the IC in an I
2
C system as I
2
C slave device. In this
system an individual reset control is not supported. The hardware reset will be executed at
power-up time (power-on reset).
Limiting values
Min
0.5
0.5
-
Max
+6.0
V
DD
+ 0.5
15.0
Unit
V
V
mA
-
15.0
mA
-
100
mA
[1]
-
4.0
kV
[2]
-
1
-
W
C
[3]
-
Fig 4.
System overview supporting Power-on Reset
001aao366
10 kΩ
PU
PU
10 kΩ
SCL
SDA
VSS
VDD
VDD
VSS
SDA
SCL
VDD
VSS
PVDD
HOST CONTROLLER
A700x
RST_N
SDA
SCL
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