參數(shù)資料
型號(hào)： A80960JA-16
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： EMBEDDED 32-BIT MICROPROCESSOR
中文描述： 32-BIT, 16 MHz, RISC PROCESSOR, CPGA132
封裝： PGA-132
文件頁(yè)數(shù)： 17/78頁(yè)
文件大小： 835K
代理商： A80960JA-16
Advance Information Datasheet
17
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3.
Pin Description — External Bus Signals (Sheet 1 of 3)
NAME
TYPE
DESCRIPTION
AD31:0
I/O
S(L)
R(X)
H(Z)
P(Q)
ADDRESS / DATA BUS
carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (
T
a
) cycle, bits 31:2 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (T
d
) cycle, read or write
data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.
SIZE, which comprises bits 0-1 of the AD lines during a
T
a
cycle, specifies the
number of data transfers during the bus transaction.
AD1
AD0
Bus Transfers
0
0
1 Transfer
0
1
2 Transfers
1
0
3 Transfers
1
1
4 Transfers
When the processor enters Halt mode, if the previous bus operation was a:
write — AD31:2 are driven with the last data value on the AD bus.
read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are
driven with the value of A3:2 from the last data cycle.
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ALE
O
R(0)
H(Z)
P(0)
ADDRESS LATCH ENABLE
indicates the transfer of a physical address. ALE is
asserted during a
T
cycle and deasserted before the beginning of the T
d
state. It is
active HIGH and floats to a high impedance state during a hold cycle (T
h
).
ALE
O
R(1)
H(Z)
P(1)
ADDRESS LATCH ENABLE
indicates the transfer of a physical address. ALE is the
inverted version of ALE. This signal gives the 80960Jx a high degree of compatibility
with existing 80960Kx systems.
ADS
O
R(1)
H(Z)
P(1)
ADDRESS STROBE
indicates a valid address and the start of a new bus access.
The processor asserts ADS for the entire
T
a
cycle. External bus control logic typically
samples ADS at the end of the cycle.
A3:2
O
R(X)
H(Z)
P(Q)
ADDRESS3:2
comprise a partial demultiplexed address bus.
32-bit memory accesses:
the processor asserts address bits A3:2 during
T
a
. The
partial word address increments with each assertion of RDYRCV during a burst.
16-bit memory accesses:
the processor asserts address bits A3:1 during
T
a
with A1
driven on the BE1 pin. The partial short word address increments with each
assertion of RDYRCV during a burst.
8-bit memory accesses:
the processor asserts address bits A3:0 during
T
a
, with A1:0
driven on BE1:0. The partial byte address increments with each assertion of
RDYRCV during a burst.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A80960JA-25 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR
A80960JA-33 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR
A80960JA3V25 功能描述:IC MPU I960JA 3V 25MHZ 132-PGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤
A80960JA3V33 功能描述:IC MPU I960JA 3V 33MHZ 132-PGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
A80960JD 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3 V EMBEDDED 32-BIT MICROPROCESSOR
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