參數(shù)資料
型號(hào): A80960JD-50
廠(chǎng)商: INTEL CORP
元件分類(lèi): 微控制器/微處理器
英文描述: 3.3 V EMBEDDED 32-BIT MICROPROCESSOR
中文描述: 32-BIT, 50 MHz, RISC PROCESSOR, CPGA132
封裝: PGA-132
文件頁(yè)數(shù): 21/78頁(yè)
文件大?。?/td> 835K
代理商: A80960JD-50
Advance Information Datasheet
21
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 5.
Pin Description — Interrupt Unit Signals
NAME
TYPE
DESCRIPTION
XINT7:0
I
A(E/L)
EXTERNAL INTERRUPT
pins are used to request interrupt service. The XINT7:0
pins can be configured in three modes:
Dedicated Mode
: Each pin is assigned a dedicated interrupt level. Dedicated inputs
can be programmed to be level (low) or edge (falling) sensitive.
Expanded Mode
: All eight pins act as a vectored interrupt source. The interrupt pins
are level sensitive in this mode.
Mixed Mode
: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act
as the five most significant bits of a vectored source. The least significant bits of the
vectored source are set to 010
2
internally.
Unused external interrupt pins should be connected to V
CC
.
NMI
I
A(E)
NON-MASKABLE INTERRUPT
causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source and is falling edge-triggered. If NMI is
unused, it should be connected to V
CC
.
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