參數(shù)資料
型號(hào)： A80960JF-25
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： EMBEDDED 32-BIT MICROPROCESSOR
中文描述： 32-BIT, 25 MHz, RISC PROCESSOR, CPGA132
封裝： PGA-132
文件頁(yè)數(shù)： 10/78頁(yè)
文件大小： 835K
代理商： A80960JF-25
80960JA/JF/JD/JT 3.3 V Microprocessor
10
Advance Information Datasheet
2.2
Burst Bus
A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory
and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit
words per six clock cycles. The external address/data bus is multiplexed.
Users may configure the 80960Jx
’s bus controller to match an application’s fundamental memory
organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and
data caching are programmed through a group of logical memory templates and a defaults register.
The BCU’s features include:
Multiplexed external bus to minimize pin count
32-, 16- and 8-bit bus widths to simplify I/O interfaces
External ready control for address-to-data, data-to-data and data-to-next-address wait state types
Support for big or little endian byte ordering to facilitate the porting of existing program code
Unaligned bus accesses performed transparently
Three-deep load/store queue to decouple the bus from the core
Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it
performs an external bus confidence test by performing a checksum on the first words of the
initialization boot record (IBR).
The user may examine the contents of the caches by executing special cache control instructions.
2.3
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several
clock rates and generating interrupts. Each is programmed by use of the TU registers. These
memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot
mode and auto-reload capabilities for continuous operation. Each timer has an independent
interrupt request to the 80960Jx
’s interrupt controller. The TU can generate a fault when
unauthorized writes from user mode are detected. Clock prescaling is supported.
2.4
Priority Interrupt Controller
A programmable interrupt controller manages up to 240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or
level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer
channels and a single Non-Maskable Interrupt (NMI) pin. Interrupts are serviced according to their
priority levels relative to the current process priority.
Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:
Interrupt vectors and interrupt handler routines can be reserved on-chip
Register frames for high-priority interrupt handlers can be cached on-chip
The interrupt stack can be placed in cacheable memory space
Interrupt microcode executes at two or three times the bus frequency for the 80960JD and
80960JT respectively
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