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參數(shù)資料
| 型號： | AAT2503IZL-BAA-T1 |
| 廠商： | Advanced Analog Technology,lnc. |
| 英文描述： | Adjustable 3-Channel Regulator |
| 中文描述： | 可調(diào)節(jié)的3通道穩(wěn)壓器 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大?。?/td> | 1022K |
| 代理商： | AAT2503IZL-BAA-T1 |
AAT2503
Adjustable 3-Channel Regulator
2503.2007.04.1.1
19
The following discussions will assume the LDO
regulator is mounted on a printed circuit board uti-
lizing the minimum recommended footprint as stat-
ed in the layout considerations section of this doc-
ument. At any given ambient temperature (T
A
), the
maximum package power dissipation can be deter-
mined by the following equation:
Constants for the AAT2503 are T
J(MAX)
(the maxi-
mum junction temperature for the device, which is
125°C) and
θ
JA
= 50°C/W (the package thermal
resistance). Typically, maximum conditions are cal-
culated at the maximum operating temperature of T
A
= 85°C and under normal ambient conditions where
T
A
= 25°C. Given T
A
= 85°C, the maximum package
power dissipation is 800mW. At T
A
= 25°C, the max-
imum package power dissipation is 2W.
The maximum continuous output current for the
AAT2503 is a function of the package power dissi-
pation and the input-to-output voltage drop across
the LDO regulator. To determine the maximum
output current for a given output voltage, refer to
the following equation. This calculation accounts
for the total power dissipation of the LDO regulator,
including that caused by ground current.
P
D(MAX)
= T
J(MAX)
- T
A
JA
P
D(MAX)
= [(V
IN
- V
OUTA
)I
OUTA
+ (V
IN
· I
GND
)] + [(V
IN
- V
OUTB
)I
OUTB
+ (V
IN
· I
GND
)]
Layout
The suggested PCB layout for the AAT2503 is
shown in Figures 2 and 3. The following guidelines
should be used to help ensure a proper layout.
1. The input capacitors (C4, C7, C8, and C9)
should connect as closely as possible to VIN
and PGND.
2. The output capacitor (C5, and C6) of the LDOs
connect as closely as possible to OUT. C2 and
L1 should be connected as closely as possible.
The connection of L1 to the LX pin should be as
short as possible. Do not make the node small
by using a narrow trace. The trace should be
kept wide, direct, and short.
3. The feedback trace should be separate from
any power trace and connect as closely as pos-
sible to the load point. Sensing along a high-
current load trace will degrade DC load regula-
tion. Feedback resistors should be placed as
closely as possible to VOUT to minimize the
length of the high impedance feedback trace. If
possible, they should also be placed away from
the LX (switching node) and inductor to
improve noise immunity.
4. The resistance of the trace from the load return
to the PGND should be kept to a minimum.
This will help to minimize any error in DC regu-
lation due to differences in the potential of the
internal signal ground and the power ground.
5. Ensure all ground pins are tied to the ground
plane. No pins should be left floating. For max-
imum power dissipation, it is recommended that
the exposed Pad must be soldered to a good
conductive PCB ground plane layer to further
increase local heat dissipation.
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