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參數(shù)資料
| 型號： | AB-026 |
| 英文描述： | AB-026 - A LOW NOISE. LOW DISTORTION DESIGN FOR ANTIALIASING AND ANTI-IMAGING FILTERS |
| 中文描述： | 抗體- 026 -甲，噪音低。低失真設(shè)計(jì)反鋸齒和反成像濾波器 |
| 文件頁數(shù)： | 8/42頁 |
| 文件大?。?/td> | 606K |
| 代理商： | AB-026 |
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8
SECTION B:
ENHANCED MACROMODELS
The enhanced version, “E”, of the standard PSpice Parts
model contains several additional performance features. All
of the macromodels using this topology are in the ENH_MOD
subdirectory on the disk. The FET-input amplifiers using the
standard PSpice Parts topology plus enhancements are shown
in Figures B1 and B2. The node assignments for the en-
hanced op amp macromodels with bipolar-inputs are shown
in Figures B3 and B4. Figure A1 shows the external op amp
node assignments. Tables II, III, and IV list component
prefix designations, macromodel component descriptions,
and PSpice INPUT designations used for the standard and
enhanced models. The parameters that are modelled by the
enhanced macromodels are listed in Table X. Additions and
changes to the standard PSpice Parts macromodel to the
enhanced version are discussed in the following text.
TABLE VII. Enhanced Macromodels Figure Reference.
See Table II, for a more detailed
description of the components.
FIGURE B1. N-Channel JFET-Input Op Amp Enhanced PSpice Parts Macromodel.
FIGURE
DESCRIPTION
B1
B2
B3
B4
B5
B6
B7
N-Channel JFET-Input Op Amp
P-Channel JFET-Input Op Amp
NPN Bipolar-Input Op Amp
PNP Bipolar-Input Op Amp
OPA27/37 Input Protection
OPA77/177 Input Protection
INA114/118 Input Protection Circuitry
Input Current Correction
One feature that Burr-Brown offers with the enhanced model
type is accurate simulation of input bias current for N-Channel
JFET and P-Channel JFET operational amplifiers. Math-
ematically, the input bias current for JFET op amps should
equal twice the I
S
of the JFET model. However, simulation
will show that the gate current from J
and J
in Figures A3
through B2 is between 10 to 20pA larger than expected,
depending on the common-mode voltage of the input stage
and the magnitude of the supply voltages, if G
and G
are
not included in the model. This additional current is gener-
ated from the drain-to-gate and source-to-gate nodes of the
input FETs of the operational amplifier, which manifests
itself as the bias current of the amplifier. The additional
current is caused by the Spice default value, GMIN. In this
case, 1/GMIN is the impedance between the drain and gate
and the source and gate. This is done by Spice to keep the
gate node of each FET from floating. The default value, or
GMIN is 1E-12
. The voltage dependent current sources,
G
11
and G
21
remove this error current from the model, hence
the macromodel models input bias current correctly. This
technique is used in all of the FET-enhanced and multiple
pole/zero
macromodels.
tion accuracy the .OPTIONS statement should include
ABSTOL = 100fA or 10fA.
To
improve
simula-
Noise
Most of the enhanced JFET-input macromodels model de-
vice current noise and voltage noise. The current noise is
modeled using R
, R
, R
, R
, R
and R
to create the
noise source and the voltage-dependent current sources, G
11
and G
21
, to model the noise on the inverting and non-
C
DIF
+
V+
V
O
V–
R
D1
R
D2
J
2
J
1
R
Q
D
P
V
C
D
C
+
V
E
D
E
4
5
3
53
54
G
CM
G
A
R
2
C
2
6
9
+
V
B
R
O1
+
E
GND
F
B
7
+
V
LIM
8
R
O2
R
SS
C
SS
99
I
SS
10
C
1
11
12
D
LN
D
LP
+
+
91
92
V
LN
V
LP
+
H
LIM
90
D
Q1
+
+
21
22
V
Q1
F
Q3
20
F
Q2
F
Q1
D
Q2
V
Q2
–In
+In
2
C
2CM
G
11
G
21
–
+
64
E
N
C
1CM
1
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