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參數(shù)資料
| 型號： | AB-123 |
| 英文描述： | AB-123 - USING THE CONTINUOUS PARALLEL MODE WITH THE ADS7824 AND ADS7825 |
| 中文描述： | 抗體- 123 -利用連續(xù)平行模式，在ADS7824與ADS7825 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 106K |
| 代理商： | AB-123 |
2
The 2x crest factor constant can be chosen to meet the
application need, however, 6.6 is the standard that Burr-
Brown has chosen to use to define “Noise Free Bits”. With
this 2x crest factor,
Noise Free Bits = Effective bits
rms – 2.723 bits.
Using the ADS1210/11 as an example, Table I illustrates
the relationship of bits
rms (FSR = 10V), Vrms, p-pV and
Noise Free Bits (FSR = 10V). In this table the data rate is
defined as the frequency of the digital output data produced
by the converter. The Turbo Mode (in this case, 16) is an
ADS1210/11 feature that is used to increase the modulator
sampling rate by 2, 4, 8 or 16 times normal. An increase
in sampling rate is equated with an increase in effective
resolution.
PROGRAM THE CONVERTER’S TURBO MODE
AND DECIMATION RATIO
The ADS1210/11 default data rate is (850
x
X
IN
7
)Hz. For
example, if the external clock to the A/D converter (X
IN
) is
10MHz, the default data rate would be 850Hz. The data rate
of the A/D converter is easily measured by putting a oscil-
loscope probe on the DRDY pin. This default data rate is
achieved with a decimation ratio of 23 (decimal) and a turbo
mode of one. When the ADS1210/11 is programmed in this
manner, the expected effective resolution is approximately
12 bits
rms (given X
IN
= 10MHz). Before 23 bits
rms of
effective resolution can be realized, the turbo mode and
decimation ratio must be re-programmed into the A/D
converter. Table III lists the suggested turbo mode and
decimation ratio vs external clock (X
IN
) that is required to
get 23 bits
rms effective resolution.
It is useful to note that the setting for the Programmable
Gain Amplifier (PGA) inside the
Σ
converter is always
configured as equal to one if 23 bits
rms of effective
resolution is the desired goal.
NOISE
LEVEL
(
μ
Vrms)
DATA
RATE
(Hz)
TURBO
MODE
RATE = 1
TURBO
MODE
RATE = 2
TURBO
MODE
RATE = 4
TURBO
MODE
RATE = 8
TURBO
MODE
RATE = 16
10
20
40
50
60
100
1000
2.9
4.3
6.9
8.1
10.5
26.9
6909.7
1.7
2.1
3.0
3.2
3.9
6.9
1.3
1.7
2.3
2.4
2.6
3.5
238.4
1.3
1.6
1.8
1.9
2.7
46.6
1.0
1.0
1.0
1.4
7.8
1354.4
TABLE II. This table demonstrates that the performance of
the ADS1210 and ADS1211 can be adjusted with changes in
Turbo mode and decimation ratio.
With the ADS1210/11, the turbo mode function allows the
user to program the over sampling speed of the converter.
The turbo mode function is the key to achieving 23 bits
rms
of effective resolution. As the turbo mode is increased, the
effective resolution is also increased. Table II shows the
relationship between Turbo Mode and various data rates.
EFFECTIVE
RESOLUTION
(p-p
μ
Vrms,
2x crest factor = 6.6)
EFFECTIVE
EFFECTIVE
NOISE
FREE BITS
DATA
RATE (Hz)
EFFECTIVE RESOLUTION
BITS
rms
(
μ
Vrms)
40
50
60
100
1000
23.0
23.0
23.0
22.5
20.0
1.0
1.0
1.0
1.4
7.8
6.6
6.6
6.6
9.24
51.48
20.28
20.28
20.28
19.78
17.28
TABLE I. Using the ADS1210/11 as an example, the various
ways of calculating the accuracy of the conversion process
are shown.
The translation from effective bits to effective resolution or
visa versa is:
ERinbitsrms
=
20log
10V
ERinVrms
6.02
–1.76
ERinVrms
=
10V
10
6.02ERinbitsrms
+
1.76
20
ACCEPTABLE
DECIMATION
RATIO(s)
EXTERNAL CLOCK
FREQUENCY, X
IN
RECOMMENDED
TURBO MODE
EXPECTED
DATA RATE (Hz)
10MHz
5MHz
2.5MHz
16
8
16
5200 to 8000
7812
7812
40Hz to 60Hz
10Hz
10Hz
TABLE III. The A/D converter’s turbo mode and decimation
ratio must be re-programmed from its default setting in order
to achieve 23 bits
rms of effective resolution.
FOLLOW GOOD GROUND AND POWER
PLANE LAYOUT PRACTICES
The best layout approach is to power the analog section of
the A/D converter from one supply and the digital section
from a separate +5V supply. In this configuration, the analog
supply should come up first insuring that the substrate is not
reverse biased causing a latch condition. Good decoupling
practices should be used for the A/D converter on both the
analog and digital supplies. A 1
μ
F to 10
μ
F capacitor, in
parallel with a 0.1
μ
F ceramic capacitor is recommended. All
decoupling capacitors should be placed as close to the
device as possible, particularly the 0.1
μ
F ceramic capaci-
tors. For either supply, high frequency noise will generally
be rejected by the digital filter except for integer multiples
of the modulator frequency. In particular, the analog supply
should be well regulated and with low noise. The Power
Supply Rejection vs Frequency graph shown in Figure 2.
The DEM-ADS1210/11 can be used to illustrate the impor-
tance of these grounding and power supply practices. Since
the segregation of the analog and digital supplies on the
power plane and ground plane is the same, the ground plane
is shown in Figure 3 and used for this discussion. The
device’s analog pins (1, 2, 3, 4, 5, 6, 7, 19, 20, 21, 22, 23, and
24 in the case of the ADS1211) are all on the analog ground
and power plane. The device’s digital pins (8, 9, 10, 11, 12,
13, 14, 15, 16, 17, and 18 in the case of the ADS1211) are
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