參數(shù)資料
型號(hào): AB-12
廠商: Fairchild Semiconductor Corporation
英文描述: Application Bulletin AB-12
中文描述: 申請(qǐng)公告抗體- 12
文件頁數(shù): 3/6頁
文件大小: 106K
代理商: AB-12
3
85.0
80.0
75.0
70.0
65.0
PSRR vs FREQUENCY
P
0.1
1
10
100
Frequency (Hz)
1k
10k
100k
FIGURE 3. The DEM-ADS1210/11 demonstration fixture analog and digital power planes are separated as shown above.
FIGURE 2. Good grounding practices and layout practices
suggest that the analog and digital power planes be separate.
The ADS1210 and ADS1211 power supply rejection versus
frequency are shown here, emphasizing that noise reduction
techniques should be applied to the power supply busses.
all on the DUT (Device Under Test) digital ground and
power plane (see Figure 3). The digital pins of the A/D
converter interface to the “DUT Controller”
μ
P, 8xC51 (U4).
This
μ
P and the “Memory Controller”
μ
P (8xC51, U5) along
with the digital memory chips have their own ground and
power plane that are partially partitioned from the DUT
digital ground and power plane. With this layout, the current
paths of the digital portion of the board are steered towards
the power connector instead of past the digital side of the A/
D converter. Power is supplied to the board via the analog
power supply connector, P4, and the digital supply connec-
tor, P5.
At first glance, this layout would suggest that the demo
board designer has gone to extraordinary efforts to optimize
the board layout for these high resolution
Σ
converters. If
the A/D converter plus a few logic chips were the only parts
on the board, the ground and power plane layout restrictions
can be relaxed. If there is a minimum amount of glue logic
in the layout, the A/D converters can achieve 23 bits of
resolution with one ground and power plane. The key to a
successful 23-bit system is to keep the digital return currents
away from the analog front end of the circuit. Pay particular
attention to the clocking network’s current paths and high
frequency coupling. Extra caution should be taken with the
surface mount versions of the ADS1210 and ADS1211.
Since the substrate of the chip is physically closer to the
board than it would be with a plastic DIP, the power plane
and ground plane should be removed from underneath the
chip.
The DEM-ADS1210/11 board lends itself for easy experi-
mentation in exploring different power layout configura-
tions. The results are summarized in Table IV.
It is useful to note that the DEM-ADS1210/11 has a fair
amount of logic on the board, including two
μ
P and an array
of memory chips. The data in Table IV illustrates the affects
of digital noise coupling into the analog signal path and
consequently increasing the noise floor.
SELECT THE RIGHT EXTERNAL CLOCK SOURCE
The type of clock that is used with the ADS121x does have
an effect on the noise performance of the device, particularly
when calibration is used. The noise seems to increase as the
clock gets further away from a perfect sine wave. For
instance, a square wave that is rich in harmonics can cause
the most problems.
A square wave is rich is harmonics which are easily coupled
from trace-to-trace or from the digital-to-analog planes.
Careful layout may reduce the affects of this noise source. In
terms of calibration, the self calibration process of the
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