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| 型號： | AB-137 |
| 英文描述： | AB-137 - ADD CURRENT LIMIT TO THE BUF634 |
| 中文描述： | 抗體- 137 -將當(dāng)前限額BUF634 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大小： | 60K |
| 代理商： | AB-137 |
1998 Burr-Brown Corporation
AB-130
Printed in U.S.A. April, 1998
1
INTERFACING THE DAC714 TO
MICRO-CONTROLLERS VIA SPI
By Gebhard Haug
The DAC714 is a complete, easy-to-use 16-bit digital to
analog converter featuring a voltage output with and a
precision reference together with a serial interface.
The suggested timing as shown in the timing diagrams of the
DAC714 data sheet makes the part difficult to use with an
SPI interface. The part seems to need 16 clock cycles to load
the serial shift register and an additional clock to update the
DAC register. Also, to update the DAC register, A1 has to be
pulled low for this clock cycle. This application note shows
an easy way to use the DAC714 on a SPI interface without
any glue logic.
Although the DAC714 contains a pin called CLK, the data
does not necessarily have to be clocked into the DAC using
this pin. A closer look at Figure 1 of the data sheet shows
that there is some combinatorial logic internal to the DAC714
before the signals are applied to the shift and DAC registers.
Instead of gating the clock signal using A0 or A1, A0 can be
used to generate the internal clock signal for the DAC714
while CLK is held low. This is an important fact if an SPI is
used to control the DAC. If the clock is used to fill in the
shift register and to update the DAC register, a total of 17
clock cycles is needed to operate the DAC properly. This is
an additional clock cycle that is difficult to generate with a
plain SPI interface. If A0 is used to shift the data into the
DAC, SCLK can be applied directly to CLK because it
needs just 16 clock cycles to shift a new value into the DAC.
The update signal can then be applied using a clr/set se-
quence of a normal port pin. In order for the DAC to operate
properly, it is best if the clock idles high between two
conversions.
The interface described can be made even easier by pulling
CLK low on all DAC714 devices or if just a single device
(the DAC) is used at the SPI port. The serial bit stream is
then shifted continuously into the D/A converters. After a
complete set of new data has been sent to the converter(s),
the update pin (A1) is toggled so the all DAC714 changes to
the new frame of data at the same time. SS can be used as
the update pin in this case because it is not needed for the
SPI communication in this scenario.
To achieve a well defined power up behavior, CLR could be
derived out of the reset circuit used for most micros. This
would insure that there is no undefined output voltage before
the controller completes its initialization routines.
Note that the same kind of interface could be done using the
synchronous serial port of 8051 style micro controllers.
Figure 1, the Motorola 68HC11 type micro controller is
interfaced to a string of DAC714s. The timing diagrams in
Figure 2 were acquired using a logic analyzer for a single
DAC714. Figure 3 is a sample program using a setup with a
single DAC714 controlled by a Motorola 68HC11. This code
can be downloaded from http://www.burr-brown.com/Prod-
ucts/DataSheets/DAC714.html
SDI
A0
CLK
A1
SDOUT
DAC714
SDI
A0
CLK
A1
SDOUT
68HC11
V
OUT
Channel 0
SDI
A0
CLK
A1
SDOUT
DAC714
V
OUT
Channel 1
SDI
A0
CLK
A1
SDOUT
DAC714
V
OUT
Channel 1
FIGURE 1. Circuit Diagrams.
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