參數(shù)資料
型號(hào): ABV8037QCL-TFREQ
廠商: ABRACON CORP
元件分類: VCXO, clock
英文描述: VCXO, CLOCK, 38 MHz - LVDS OUTPUT
封裝: QFN
文件頁(yè)數(shù): 9/10頁(yè)
文件大?。?/td> 215K
代理商: ABV8037QCL-TFREQ
(Preliminary)
ABV8037/38/39
38MHz-320MHz Low Phase Noise VCXO
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 9/1/05 Page 8
LAYOUT RECOMMENDATIONS
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to ABV80 as short as
possible, as well as keeping all other traces as
far away from it as possible.
- Place the crystal as close as possible to both
crystal pins of the device. This will reduce the
cross-talk between the crystal and the other
signals.
- Separate crystal pin traces from the other signals
on the PCB, but allow ample distance between
the two crystal pin traces.
- Place a 0.01F~0.1F decoupling capacitor
between VDD and GND, on the component side
of the PCB, close to the VDD pin. It is not
recommended to place this component on the
backside of the PCB. Going through vias will
reduce the signal integrity, causing additional
jitter and phase noise.
- It is highly recommended to keep the VDD and
GND traces as short as possible.
- When connecting long traces (> 1 inch) to a
CMOS output, it is important to design the traces
as a transmission line or ‘stripline’, to avoid
reflections or ringing. In this case, the CMOS
output needs to be matched to the trace
impedance. Usually ‘striplines’ are designed for
50 impedance and CMOS outputs usually have
lower than 50 impedance so matching can be
achieved by adding a resistor in series with the
CMOS output pin to the ‘stripline’ trace.
- Please contact Abracon for the application note
on how to design outputs driving long traces or
the Gerber files for the ABV80 layout.
ABV803X
(VCXO)
16 pin TSSOP
ABV803X
(VCXO)
3x3 QFN
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