參數(shù)資料
型號(hào): ACE1101E
廠商: Fairchild Semiconductor Corporation
英文描述: Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
中文描述: 算術(shù)控制器引擎(ACEx⑩)的低功耗應(yīng)用
文件頁(yè)數(shù): 14/33頁(yè)
文件大小: 152K
代理商: ACE1101E
14
www.fairchildsemi.com
ACE1101 Rev. C.8
A
4.0 Arithmetic Controller Core
The ACE1101 core is specifically designed for low cost applica-
tions involving bit manipulation, shifting and block encryption. It is
based on a modified Harvard architecture meaning peripheral,
I/O, and RAM locations are addressed separately from instruction
data.
The core differs from the traditional Harvard architecture by
aligning the data and instruction memory sequentially. This allows
the X-pointer (11-bits) to point to any memory location in either
Figure 12: Programming Model
8-bit accumulator register
11-bit X pointer register
10-bit program counter
4-bit stack pointer
8-bit status register
NEGATIVE flag
HALF CARRY flag (from bit 3)
CARRY flag (from MSB)
ZERO flag
GLOBAL Interrupt Mask
READY flag (from EEPROM)
A
X
PC
SP
SR
0
0
0
0
N
H
C
Z
G
0
0
R
7
10
9
3
segment of the memory map. This modification improves the
overall code efficiency of the ACE1101 and takes advantage of
the flexibility found on Von Neumann style machines.
4.1 CPU Registers
The ACE1101 has five general purpose registers. They are the A,
X, PC, SP, and SR. The X, SP and SR are memory mapped
registers.
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