參數(shù)資料
型號: ACE1202EN
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
中文描述: 8-BIT, EEPROM, 1 MHz, MICROCONTROLLER, PDIP8
封裝: DIP-8
文件頁數(shù): 24/39頁
文件大?。?/td> 2121K
代理商: ACE1202EN
24
www.fairchildsemi.com
ACE1202 Product Family Rev. B.1
A
6.0 Timer 0
Timer 0 is a 12-bit free running idle timer. Upon power-up or any
reset, the timer is reset to 0x000 and then counts up continuously
based on the instruction clock of 1MHz (1
μ
s). Software cannot
read from or write to this timer. However, software can monitor the
timer
s pending (T0PND) bit that is set every 8192 cycles (initially
4096 cycles after a reset). The T0PND flag is set every other time
the timer overflows (transitions from 0xFFF to 0x000) through a
divide-by-2 circuit. After an overflow, the timer will reset and restart
its counting sequence.
Software can either poll the T0PND bit or vector to an interrupt
subroutine. In order to interrupt on a T0PND, software must be
sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the
Timer 0 control (T0CNTRL) register and also make sure the G bit
is set in SR. Once the timer interrupt is serviced, software should
reset the T0PND bit before exiting the routine. Timer 0 supports
the following functions:
1. Exiting from IDLE mode (See Section 17.0 for details.)
2. Start up delay from HALT mode
3. Watchdog pre-scaler (See Section 7.0 for details.)
The T0INTEN bit is a read/write bit. If set to 0, interrupt requests
from the Timer 0 are ignored. If set to 1, interrupt requests are
accepted. Upon reset, the T0INTEN bit is reset to 0.
The T0PND bit is a read/write bit. If set to 1, it indicates that a Timer
0 interrupt is pending. This bit is set by a Timer 0 overflow and is
Figure 19: Timer 0 Control Register (T0CNTRL)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WKINTEN
x
x
x
x
x
T0PND
T0INTEN
Figure 20: Watchdog Server Register (WDSVR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
1
0
1
1
reset by software or system reset.
The WKINTEN bit is used in the Multi-input Wakeup/Interrupt
block. See Section 8 for details.
7.0 Watchdog timer
The Watchdog timer is used to reset the device and safely recover
in the rare event of a processor
runaway condition.
The 12-bit
Timer 0 is used as a pre-scaler for Watchdog timer. The Watchdog
timer must be serviced before every 61,440 cycles but no sooner
than 4096 cycles since the last Watchdog reset. The Watchdog is
serviced through software by writing the value 0x1B to the
Watchdog Service (WDSVR) register (see Figure 20). The part
resets automatically if the Watchdog is serviced too frequent, or
not frequent enough.
The Watchdog timer must be enabled through the Watchdog
enable bit (WDEN) in the initialization register. The WDEN bit can
only be set while the device is in programming mode. Once set, the
Watchdog will always be powered-up enabled. Software cannot
disable the Watchdog. The Watchdog timer can only be disabled
in programming mode by resetting the WDEN bit as long as the
memory write protect (WDIS) feature is not enabled.
WARNING
Ensure that the Watchdog timer has been serviced before enter-
ing IDLE mode because it remains operational during this time.
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ACE1202EN8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
ACE1202L 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
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ACE1202LEM8X 功能描述:8位微控制器 -MCU arithmetic Controllr Engine RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT