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參數(shù)資料
| 型號(hào)： | ACPL-M72T-060E |
| 元件分類： | 光電耦合器 |
| 英文描述： | 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER |
| 封裝： | ROHS COMPLIANT, SURFACE MOUNT, SOIC-5 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 114K |
| 代理商： | ACPL-M72T-060E |
7
ACPL-M72T Low Power Mode Switching Specifications
Over recommended temperature (-40°C to +125°C), 3.0V ≤ VDD ≤ 5.5V. All typical specifications at +25°C and VDD = 5V
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig
Note
Propagation Delay Time to
Logic Low Output[1]
tPHL
60
100
ns
IF=4mA, CL=15pF
7,8,
9,10,
14
1,2,3
Propagation Delay Time to
Logic High Output[1]
tPLH
35
100
ns
Pulse Width Distortion[2]
PWD
25
50
ns
Propagation Delay Skew[3]
tPSK
60
ns
Output Rise Time
(10% – 90%)
tR
10
ns
Output Fall Time
(90% - 10%)
tF
10
ns
Common Mode Transient
Immunity at Logic High
Output[4]
| CMH |25
40
kV/
s
Using Avago LED Driving
Circuit,
VIN=0V, R1=350
+/-5% ,
R2=350
+/-5%, VCM=1000V,
TA=25°C
15
4
Common Mode Transient
Immunity at Logic High
Output[5]
| CML |25
40
kV/
s
Using Avago LED Driving
Circuit,
VIN=4.5-5.5V, R1=350
+/-5% ,
R2=350
, VCM=1000V, TA=25°C
16
5
Package Characteristics
All Typical at TA = 25°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Input-Output Momentary
Withstand Voltage
VISO
4000
Vrms
RH ≤ 50%, t = 1 min.,
TA = 25°C
Input-Output Resistance
R I-O
1014
VI-O = 500 V dc
Input-Output Capacitance
C I-O
0.6
pF
f = 1 MHz, TA = 25°C
Notes:
1. tPHL propagation delay is measured from the 50% (Vin or If ) on the rising edge of the input pulse to 0.8V on the falling edge of the VO signal. tPLH
propagation delay is measured from the 50% (Vin or If ) on the falling edge of the input pulse to the 80% level of the rising edge of the VO signal.
2. PWD is defined as |tPHL - tPLH|.
3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
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