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參數(shù)資料
| 型號： | ACPL-P611-060E |
| 元件分類： | 光電耦合器 |
| 英文描述： | 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10 Mbps |
| 封裝： | ROHS COMPLIANT, SOP-6 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 143K |
| 代理商： | ACPL-P611-060E |
8
Switching Specications (AC)
Over recommended operating conditions T
A
= -40°C to 85°C, V
CC
= 5 V, I
F
= 7.5 mA unless otherwise specied.
All typicals at V
CC
= 5 V, T
A
= 25 °C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay Time to
t
PLH
20
48
75
ns
T
A
= 25°C
R
L
= 350 Ω,
5
High Output Level
100
C
L
= 15 pF
Propagation Delay Time to
t
PHL
25
50
75
ns
T
A
= 25°C
6
Low Output Level
100
Pulse Width Distortion
|t
PHL
- t
PLH
|
3.5
35
ns
R
L
= 350 Ω,
10
C
L
= 15 pF
Propagation Delay Skew
t
PSK
40
ns
10, 11
Output Rise Time (10%-90%)
t
R
24
ns
Output Fall Time (10%-90%)
t
F
10
ns
Output High Level Common
|CM
H
|
10
15
kV/μs
V
CC
= 5 V, I
F
= 0 mA,
7, 9
Mode Transient Immunity
V
O(MIN)
= 2 V,
R
L
= 350 Ω,
T
A
= 25°C,
V
CM
= 1000 V
Output Low Level Common
|CM
L
|
10
15
kV/μs
V
CC
= 5 V, I
F
= 7.5 mA,
8, 9
Mode Transient Immunity
V
O(MAX)
= 0.8 V,
R
L
= 350 Ω,
T
A
= 25°C,
V
CM
= 1000 V
Package Characteristics
All typicals at T
A
= 25 °C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Input-Output Insulation
V
ISO
3750
V
rms
RH < 50% for 1 min.
3, 4
T
A
= 25°C
Input-Output Resistance
R
I-O
1012
Ω
V
I-O
= 500 V
3
Input-Output Capacitance
C
I-O
0.6
pF
f = 1 MHz, T
A
= 25 °C
3
Notes:
1.
Bypassing of the power supply line is required with a 0.1 μF ceramic disc capacitor adjacent to each optocoupler. The total lead length be-
tween both ends of the capacitor and the isolator pins should not exceed 10 mm.
2.
Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
3.
Device considered a two terminal device: pins 1, 2 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4.
In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
RMS
for 1 second (Leakage de-
tection current limit, I
I-O
≤ 5 μA).
5.
The t
PLH
propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the
output pulse.
6.
The t
PHL
propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the
output pulse.
7.
CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state
(i.e., V
OUT
> 2.0 V).
8.
CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., V
OUT
> 0.8 V).
9.
For sinusoidal voltages, (|dV
CM
|/dt)
max
=
Sf
CM
V
CM(p-p)
.
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. t
PSK
is equal to the worst case dierence in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within the worst case
operating condition range.
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