參數(shù)資料
型號: ACS30DMSR-03
廠商: INTERSIL CORP
元件分類: 通用總線功能
英文描述: ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
中文描述: 8-INPUT NAND GATE, CDIP14
封裝: SIDE BRAZED, CERAMIC, DIP-14
文件頁數(shù): 2/2頁
文件大?。?/td> 38K
代理商: ACS30DMSR-03
2
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Die Characteristics
DIE DIMENSIONS:
Size: 2390
μ
m x 2390
μ
m (94 mils x 94 mils)
Thickness: 525
μ
m
±
25
μ
m (20.6 mils
±
1 mil)
Bond Pad: 110
μ
m x 110
μ
m (4.3 x 4.3 mils)
METALLIZATION: AI
Metal 1 Thickness: 0.7
μ
m
±
0.1
μ
m
Metal 2 Thickness: 1.0
μ
m
±
0.1
μ
m
SUBSTRATE POTENTIAL
Unbiased Insulator
PASSIVATION:
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30
μ
m
±
0.15
μ
m
SPECIAL INSTRUCTIONS
Bond V
CC
First
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 10
5
A/cm
2
Transistor Count: 86
Metallization Mask Layout
ACS30MS
B
(2)
A
(1)
V
CC
(14)
C (3)
D (4)
NC
E (5)
(12) H
(11) G
NC
NC
(6)
F
(7)
GND
(8)
Y
NC
NC
ACS30MS
相關PDF資料
PDF描述
ACS30K Radiation Hardened 8-Input NAND Gate
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ACS32MS Radiation Hardened Quad 2-Input OR Gate(抗輻射四2輸入或門)
ACS32DMSR-03 Radiation Hardened Quad 2-Input OR Gate
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