參數(shù)資料
型號： ACS8946T
廠商： Semtech
文件頁數(shù)： 36/40頁
文件大?。?/td> 0K
描述： IC JITTER ATT MULT PLL 48-QFN
標(biāo)準(zhǔn)包裝： 1
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： LVPECL
輸出： CML，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 625MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN（7x7）
包裝： 托盤
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 5
www.semtech.com
ACS8946 JAM PLL
15
CFG_OUT2
O
LVTTL/
LVCMOS
Configuration pin, used in the configuration on power-up of expected input clock
frequency and Resync selection, by connecting to appropriate pin from the CFG_IN[0:7]
pins as required. See “Configuration” on page 13.
16
ALARMC_CO3
O
LVTTL/
LVCMOS
Activity alarm output for the currently selected input reference clock. Active high; high
indicating clock failure. It is also used to configure the device at power-up, where it is
used as a configuration output pin that may be connected to CFG_IN[0:7] input pins as
17
LOCKB
O
Analog
Lock detect output. This is a pulse-width modulated output current, with each pulse
typically +10
A. The output produces a pulse with a width in proportion to the phase
error seen at the internal phase detector. This pin should be connected via an external
parallel capacitor and resistor to ground. The pin voltage will then give an indication of
phase lock: When low, the device is phase locked; when high the device has frequent
large phase errors and so is not phase locked. The value of the RC components used
determines the time and level of consistency required for lock indication. If LOCKB is
disabled by configuration the LOCKB output is held low.
18
CFG_IN0
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 19
to set the available output rates as shown in Table 11.
19
CFG_IN1
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 18
to set the available output rates as shown in Table 11.
20
CFG_IN2
I
LVTTL/
LVCMOSD
Schmitt
Trigger
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 21
to set the input divider and output pad mode (CML or LVPECL) configuration for OUT1
and OUT2 as in Table 10.
21
CFG_IN3
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 20
to set the input divider and output pad mode (CML or LVPECL) configuration for OUT1
and OUT2 as in Table 10.
22
CFG_IN4
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 23 to
set the clock edge used for SYNC sampling, and the output clock frequency of OUT3 (pins
8 and 9) and OUT4 (pins 11 and 12), as shown in Table 12.
23
CFG_IN5
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 22 to
set the clock edge used for SYNC sampling, and the output clock frequency of OUT3 (pins
8 and 9) and OUT4 (pins 11 and 12), as shown in Table 12.
Table 3 Functional Pins (cont...)
Pin No.
Symbol
I/O
Type
Description
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