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參數(shù)資料
| 型號(hào)： | ACT-5261PC-133F17C |
| 廠商： | Aeroflex Inc. |
| 英文描述： | ACT 5261 64-Bit Superscaler Microprocessor |
| 中文描述： | 法5261 64位微處理器Superscaler |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 170K |
| 代理商： | ACT-5261PC-133F17C |
Features
eroflex Circuit Technology – RISC TurboEngines For The Future SCD5261 REV 1 12/22/98
Block Diagram
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Full militarized QED RM5261 microprocessor
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Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
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133, 150, 200, 250 MHz operating frequencies – Consult Factory
for latest speeds
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345 Dhrystone 2.1 MIPS
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SPECInt95 7.3, SPECfp95 8.3
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Pinout compatible with popular RM5260
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High performance system interface compatible with RM5260,
RM 5270, RM5271, RM7000, R4600, R4700 and R5000
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64-bit multiplexed system address/data bus for optimum price/
performance
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High performance write protocols maximize uncached write
bandwidth
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Supports 1/2 clock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)
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IEEE 1149.1 JTAG boundary scan
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Integrated on-chip caches
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32KB instruction - 2 way set associative
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32KB data - 2 way set associative
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Pipeline restart on first double for data cache misses
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Integrated memory management unit
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Fully associative joint TLB (shared by I and D translations)
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48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
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High-performance floating point unit: up to 500 MFLOPS
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Single cycle repeat rate for common single precision operations
and some double precision operations
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Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
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Single cycle repeat rate for single precision combined multiply-
add operation
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MIPS IV instruction set
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Floating point multiply-add instruction increases performance in
signal processing and graphics applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
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Embedded application enhancements
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Specialized DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
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Fully static CMOS design with power down logic
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Standby reduced power mode with WAIT instruction
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3.6 Watts typical power @ 200MHz
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2.5V core with 3.3V IO’s
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208-lead CQFP, cavity-up package (F17)
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208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
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179-pin PGA package (
Future Product) (P10)
Preliminary
64-Bit Superscaler Microprocessor
ACT 5261
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACT-5261PC-133F17I | ACT 5261 64-Bit Superscaler Microprocessor |
| ACT-5261PC-133F17M | ACT 5261 64-Bit Superscaler Microprocessor |
| AEE02A12-4 | 1-OUTPUT 10 W DC-DC REG PWR SUPPLY MODULE |
| AIPT-92-100-2.6H | 1 ELEMENT, 94.1 uH, GENERAL PURPOSE INDUCTOR |
| AIPT-92-100-3.6V | 1 ELEMENT, 90.7 uH, GENERAL PURPOSE INDUCTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACT-5261PC-133F17I | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 5261 64-Bit Superscaler Microprocessor |
| ACT-5261PC-133F17M | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 5261 64-Bit Superscaler Microprocessor |
| ACT-5261PC-133F17Q | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 5261 64-Bit Superscaler Microprocessor |
| ACT-5261PC-133F17T | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 5261 64-Bit Superscaler Microprocessor |
| ACT-5261PC-133F24C | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT 5261 64-Bit Superscaler Microprocessor |
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