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參數(shù)資料
| 型號： | ACT-SF512K16N-37F18T |
| 廠商： | Aeroflex Inc. |
| 英文描述： | Serial-out shift registers 16-SO 0 to 70 |
| 中文描述： | 行為SF512K16高速512Kx16的SRAM /閃存多芯片模塊 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 168K |
| 代理商： | ACT-SF512K16N-37F18T |
Aeroflex Circuit Technology
SCD1663 REV A 4/28/98 Plainview NY (516) 694-6700
4
Timing Diagrams — SRAM
D
I/O
t
RC
t
OH
t
AA
Data Valid
Previous Data Valid
t
OE
High Z
t
OHZ
Read Cycle Timing Diagrams
Data Valid
t
CLZ
SCE
OE
t
ACE
t
CHZ
UNDEFINED
DON’T CARE
Read Cycle 2 (SWE = V
IH
)
Write Cycle (SCE Controlled, OE = V
IH
)
t
CW
t
AS
t
WP
t
DW
t
OW
t
DH
SCE
SWE
Data Valid
Write Cycle (SWE Controlled, OE = V
IH
)
D
I/O
AC Test Circuit
I
OL
Parameter
Input Pulse Level
Input Rise and Fall
Input and Output Timing Reference
Typical
0 – 3.0
5
1.5
Units
V
ns
V
Notes:
1) V
Z
is programmable from -2V to +7V. 2) I
OL
and I
OH
programmable from 0 to 16 mA. 3) Tester Impedance
Z
O
= 75
. 4)
V
Z
is typically the midpoint of V
OH
and V
OL
. 5) I
OL
and I
OH
are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
I
OH
To Device Under Test
V
Z
~ 1.5 V (Bipolar Supply)
Current Source
Current Source
C
L
= 50 pF
t
WC
t
AW
t
AH
t
RC
t
AA
t
OLZ
S
EE
N
OTE
S
EE
N
OTE
S
EE
OTE
S
EE
N
OTE
Note: Guaranteed by design, but not tested.
D
I/O
t
OTE
S
EE
N
Read Cycle 1 (SCE = OE = V
IL
, SWE = V
IH
)
Write Cycle Timing Diagrams
t
WP
t
DW
Data Valid
t
WC
t
AW
t
AH
D
I/O
t
DH
SCE
SWE
t
CW
t
AS
A
0-18
A
0-18
A
0-18
A
0-18
AC Test Conditions
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|---|---|
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