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參數(shù)資料
| 型號(hào)： | ACTS112D |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Dual J-K Flip-Flop |
| 中文描述： | 輻射加固雙JK觸發(fā)器 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 237K |
| 代理商： | ACTS112D |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
ACTS112MS
Radiation Hardened
Dual J-K Flip-Flop
Pinouts
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CP1
K1
J1
S1
Q1
Q1
GND
Q2
VCC
R2
CP2
K2
J2
S2
Q2
R1
CP1
K1
J1
S1
Q1
Q1
Q2
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
VCC
R1
R2
CP2
K2
J2
S2
Q2
Features
Devices QML Qualified in Accordance with MIL-PRF-38535
Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96714 and Intersil’s QM Plan
1.25 Micron Radiation Hardened SOS CMOS
Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
Dose Rate Survivability. . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current
≤
1
μ
A at VOL, VOH
Fast Propagation Delay. . . . . . . . . . . . . . . . 26ns (Max), 16ns (Typ)
Description
The Intersil ACTS112MS is a Radiation Hardened Dual J-K Flip-Flop
with Set and Reset. The output change states on the negative transition
of the clock (CP1N or CP2N).
The ACTS112MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line Package (D suffix).
January 1996
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9671401VEC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
16 Lead SBDIP
5962F9671401VXC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
16 Lead Ceramic Flatpack
ACTS112D/Sample
25
o
C
Sample
16 Lead SBDIP
ACTS112K/Sample
25
o
C
Sample
16 Lead Ceramic Flatpack
ACTS112HMSR
25
o
C
Die
Spec Number
518825
File Number
3570.1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACTS112K | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| ACTS112MS | Radiation Hardened Dual J-K Flip-Flop |
| ACTS112HMSR | Radiation Hardened Dual J-K Flip-Flop |
| ACTS125D | Radiation Hardened Quad Buffer, Three-State |
| ACTS125K | Radiation Hardened Quad Buffer, Three-State |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACTS112HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop |
| ACTS112K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop |
| ACTS112MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop |
| ACTS125D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad Buffer, Three-State |
| ACTS125HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad Buffer, Three-State |
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