參數(shù)資料
型號(hào): ACTS125MS
廠商: Intersil Corporation
英文描述: ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
中文描述: 輻射加固四緩沖,三態(tài)
文件頁(yè)數(shù): 1/4頁(yè)
文件大?。?/td> 42K
代理商: ACTS125MS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
ACTS125MS
Radiation Hardened
Quad Buffer, Three-State
Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14,
LEAD FINISH C
TOP VIEW
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14
LEAD FINISH C
TOP VIEW
OE1
A1
Y1
OE2
A2
Y2
GND
VCC
OE4
A4
Y4
OE3
A3
Y3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
OE1
A1
Y1
OE2
A2
Y2
GND
VCC
OE4
A4
Y4
OE3
A3
Y3
Features
Devices QML Qualified in Accordance with MIL-PRF-38535
Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96715 and Intersil’ QM Plan
1.25 Micron Radiation Hardened SOS CMOS
Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
Dose Rate Survivabilty . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current
1
μ
A at VOL, VOH
Fast Propagation Delay. . . . . . . . . . . . . . . . 17ns (Max), 11ns (Typ)
Description
The Intersil ACTS125MS is a Radiation Hardened Quad Buffer with
Three-State outputs. Each output has it’s own enable input, which when
“HIGH” puts the output in a high impedance state.
The ACTS125MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS125MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
January 1996
Spec Number
518826
File Number
3566.1
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9671501VCC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
14 Lead SBDIP
5962F9671501VXC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
14 Lead Ceramic Flatpack
ACTS125D/Sample
25
o
C
Sample
14 Lead SBDIP
ACTS125K/Sample
25
o
C
Sample
14 Lead Ceramic Flatpack
ACTS125HMSR
25
o
C
Die
Die
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