參數(shù)資料
型號(hào)： ACTS280MS
廠商： Intersil Corporation
英文描述： Radiation Hardened 9-Bit Odd/ Even Parity Generator Checker
中文描述： 輻射加固9位單/雙校驗(yàn)發(fā)生器檢查
文件頁(yè)數(shù)： 1/4頁(yè)
文件大?。?/td> 57K
代理商： ACTS280MS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
ACTS280MS
Radiation Hardened 9-Bit Odd/
Even Parity Generator Checker
Features
Devices QML Qualified in Accordance with MIL-PRF-38535
Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96720 and Intersil’ QM Plan
1.25 Micron Radiation Hardened SOS CMOS
Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
Dose Rate Survivability. . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current
≤
1
μ
A at VOL, VOH
Fast Propagation Delay. . . . . . . . . . . . . . . . 24ns (Max), 16ns (Typ)
Description
The Intersil ACTS280MS is a Radiation Hardened 9-bit odd/even parity
generator checker device. Both odd and even parity outputs are available
for generating or checking parity for words up to 9 bits long. Even parity
is indicated (EVEN output high) when an even number of data inputs are
high. Odd parity is indicated (ODD output high) when an odd number of
data inputs are high. Parity checking for larger words can be accom-
plished by tying EVEN output to any input of an additional ACTS280MS.
The ACTS280MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS280MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line Package (D suffix).
January 1996
Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14,
LEAD FINISH C
TOP VIEW
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14
LEAD FINISH C
TOP VIEW
I6
I7
NC
I8
EVEN
ODD
GND
VCC
I5
I4
I3
I2
I1
I0
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
I6
I7
NC
I8
EVEN
ODD
GND
VCC
I5
I4
I3
I2
I1
I0
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9672001VCC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
14 Lead SBDIP
5962F9672001VXC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
14 Lead Ceramic Flatpack
ACTS280D/Sample
25
o
C
Sample
14 Lead SBDIP
ACTS280K/Sample
25
o
C
Sample
14 Lead Ceramic Flatpack
ACTS280HMSR
25
o
C
Die
Die
Spec Number
518827
File Number
3569.1
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