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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
ACTS374MS
Radiation Hardened
Octal D Flip-Flop, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T20, LEAD FINISH C
TOP VIEW
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP4-F20, LEAD FINISH C
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
VCC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
CP
2
3
4
5
6
7
8
9
10
1
20
19
18
17
16
15
14
13
12
11
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
April 1995
Truth Table
INPUTS
OUTPUTS
OE
L
L
L
H
CP
Dn
H
L
X
X
Qn
H
L
Q0
Z
X
X
H = High Level
L = Low Level
X = Immaterial
Z = High Impedance
= Transition from Low to High Level
= the level of Q before the indicated input conditions
were established
Q0
Functional Diagram
D
Q
CP
D
CP
Q
OE
FF
COMMON CONTROLS
OE
1 OF 8
Ordering Information
PART NUMBER
ACTS374DMSR
ACTS374KMSR
ACTS374D/Sample
ACTS374K/Sample
ACTS374HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Spec Number
518828
File Number
3998
Features
1.25 Micron Radiation Hardened SOS CMOS
Total Dose 300K RAD (Si)
Single Event Upset (SEU) Immunity
<1 x 10
-10
Errors/Bit-Day (Typ)
SEU LET Threshold >80 MEV-cm
2
/mg
Dose Rate Upset >10
11
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2V Min
Input Current
≤
1
μ
A at VOL, VOH
Description
The Intersil ATCS374MS is a radiation hardened octal D-type
flip-flop with three-state outputs. The eight edge-triggered flip-
flops enter data into their registers on the low to high transition of
clock (CP). The Output Enable (OEN) controls the three-state
outputs and is independent of the register operation. When OEN
is high, the outputs will be in the high impedance state.
The ACTS374MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.