參數(shù)資料
型號(hào): ACTS74K
廠商: Intersil Corporation
英文描述: Radiation Hardened Dual D Flip Flop with Set and Reset
中文描述: 輻射硬化的設(shè)置和復(fù)位雙D觸發(fā)器拖鞋
文件頁數(shù): 1/3頁
文件大?。?/td> 115K
代理商: ACTS74K
1
TM
ACTS74MS
Radiation Hardened Dual D
Flip Flop with Set and Reset
Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14,
LEAD FINISH C
TOP VIEW
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP3-F14,
LEAD FINISH C
TOP VIEW
R1
D1
CP1
S1
Q1
Q1
GND
VCC
R2
D2
CP2
S2
Q2
Q2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
R1
D1
CP1
S1
Q1
Q1
GND
VCC
R2
D2
CP2
S2
Q2
Q2
Features
Devices QML Qualified in Accordance with MIL-PRFF-38535
Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96713 and Intersil’s QM Plan
1.25 Micron Radiation Hardened SOS CMOS
Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
Dose Rate Survivability. . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Significant Power Reduction Compared to ALSTTL Logic
DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current
1
μ
A at VOL, VOH
Fast Propagation Delay. . . . . . . . . . . . . . . . 20ns (Max), 13ns (Typ)
Description
The Intersil ACTS74MS is a Radiation Hardened Dual D Flip Flop with
Set(s) and Reset (R). The logic level at data input is transferred to the
output during the positive transition of the clock. The Set and Reset are
independent from the clock and accomplished by a low level on the
appropriate input.
The ACTS74MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS74MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
14 Lead Ceramic Dual-In-Line Package (D suffix).
January 1996
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9671301VCC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
14 Lead SBDIP
5962F9671301VXC
-55
o
C to +125
o
C
MIL-PRF-38535 Class V
14 Lead Ceramic Flatpack
ACTS74D/Sample
25
o
C
Sample
14 Lead SBDIP
ACTS74K/Sample
25
o
C
Sample
14 Lead Ceramic Flatpack
ACTS74HMSR
25
o
C
Die
Die
Spec Number
518787
File Number
3382.1
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, All Rights Reserved
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參數(shù)描述
ACTS74MS 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual D Flip Flop with Set and Reset
ACTS86D 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input Exclusive OR Gate
ACTS86DMSR 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input Exclusive OR Gate
ACTS86HMSR 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input Exclusive OR Gate
ACTS86K 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input Exclusive OR Gate